fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-21 18:00:13 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965: require pixel scoreboard stall prior to ISP disable

Browse source 
Invalidating the indirect state pointers might affect a previously
scheduled & still running 3DPRIMITIVE (causing page fault). So stall
on pixel scoreboard before that.

v2: Fix compile issue :(

v3: Stall on pixel scoreboard

v4: Drop the post sync operation (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Fixes: ca19ee33d7 ("i965/gen10: Ignore push constant packets during context restore.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106243
This commit is contained in:
Lionel Landwerlin 2018-05-01 12:32:45 +01:00
parent 561348caa1
commit f536097f67
1 changed files with 8 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
src/mesa/drivers/dri/i965/brw_pipe_control.c
View file

@ -349,14 +349,21 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw)
* context restore, so the mentioned hang doesn't happen. However, * context restore, so the mentioned hang doesn't happen. However,
* software must program push constant commands for all stages prior to * software must program push constant commands for all stages prior to
* rendering anything, so we flag them as dirty. * rendering anything, so we flag them as dirty.
*
* Finally, we also make sure to stall at pixel scoreboard to make sure the
* constants have been loaded into the EUs prior to disable the push constants
* so that it doesn't hang a previous 3DPRIMITIVE.
*/ */
void void
gen10_emit_isp_disable(struct brw_context *brw) gen10_emit_isp_disable(struct brw_context *brw)
{ {
brw_emit_pipe_control(brw, brw_emit_pipe_control(brw,
PIPE_CONTROL_ISP_DIS | PIPE_CONTROL_STALL_AT_SCOREBOARD |
PIPE_CONTROL_CS_STALL, PIPE_CONTROL_CS_STALL,
NULL, 0, 0); NULL, 0, 0);
brw_emit_pipe_control(brw,
PIPE_CONTROL_ISP_DIS,
NULL, 0, 0);
brw->vs.base.push_constants_dirty = true; brw->vs.base.push_constants_dirty = true;
brw->tcs.base.push_constants_dirty = true; brw->tcs.base.push_constants_dirty = true;