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anv: ensure mesh pipeline have all pre-rasterization stages disabled

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 44656f98d5 ("anv: split pipeline programming into instructions")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>
This commit is contained in:
Lionel Landwerlin 2023-09-08 09:37:12 +03:00 • committed by Marge Bot
parent 80feff8559
commit f5344a6b1c
1 changed files with 8 additions and 2 deletions
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10
src/intel/vulkan/genX_pipeline.c
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@ -1937,6 +1937,8 @@ genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline,
}
#endif
emit_3dstate_vf_statistics(pipeline);
if (anv_pipeline_is_primitive(pipeline)) {
emit_vertex_input(pipeline, state, state->vi);
@ -1945,8 +1947,6 @@ genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline,
emit_3dstate_te(pipeline);
emit_3dstate_gs(pipeline);
emit_3dstate_vf_statistics(pipeline);
emit_3dstate_streamout(pipeline, state->rs);
#if GFX_VERx10 >= 125
@ -1962,6 +1962,12 @@ genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline,
} else {
assert(anv_pipeline_is_mesh(pipeline));
anv_pipeline_emit(pipeline, final.vs, GENX(3DSTATE_VS), vs);
anv_pipeline_emit(pipeline, final.hs, GENX(3DSTATE_HS), hs);
anv_pipeline_emit(pipeline, final.ds, GENX(3DSTATE_DS), ds);
anv_pipeline_emit(pipeline, partial.te, GENX(3DSTATE_TE), te);
anv_pipeline_emit(pipeline, partial.gs, GENX(3DSTATE_GS), gs);
/* BSpec 46303 forbids both 3DSTATE_MESH_CONTROL.MeshShaderEnable
* and 3DSTATE_STREAMOUT.SOFunctionEnable to be 1.
*/