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i965: add a new virtual opcode: SHADER_OPCODE_TXF_MS

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This is very similar to the TXF opcode, but lowers to `ld2dms` rather
than `ld` on Gen7.

V4: - add SHADER_OPCODE_TXF_MS to is_tex() functions, so regalloc thinks
      it actually writes the correct number of registers. Otherwise in
      nontrivial shaders some of the registers tend to get clobbered,
      producing bad results.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
This commit is contained in:
Chris Forbes 2013-01-24 21:35:15 +13:00
parent 555dc6d74d
commit f52ce6a0ca
5 changed files with 18 additions and 0 deletions
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1
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -709,6 +709,7 @@ enum opcode {
SHADER_OPCODE_TXL,
SHADER_OPCODE_TXS,
FS_OPCODE_TXB,
SHADER_OPCODE_TXF_MS,
SHADER_OPCODE_SHADER_TIME_ADD,

2
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -336,6 +336,7 @@ fs_inst::is_tex()
opcode == FS_OPCODE_TXB ||
opcode == SHADER_OPCODE_TXD ||
opcode == SHADER_OPCODE_TXF ||
opcode == SHADER_OPCODE_TXF_MS ||
opcode == SHADER_OPCODE_TXL ||
opcode == SHADER_OPCODE_TXS);
}
@ -740,6 +741,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
case FS_OPCODE_TXB:
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
return 1;

7
src/mesa/drivers/dri/i965/brw_fs_emit.cpp
View file

@ -398,6 +398,12 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
case SHADER_OPCODE_TXF:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_MS:
if (intel->gen >= 7)
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
else
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
default:
assert(!"not reached");
break;
@ -1236,6 +1242,7 @@ fs_generator::generate_code(exec_list *instructions)
case FS_OPCODE_TXB:
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
generate_tex(inst, dst, src[0]);

1
src/mesa/drivers/dri/i965/brw_vec4.cpp
View file

@ -146,6 +146,7 @@ vec4_instruction::is_tex()
return (opcode == SHADER_OPCODE_TEX ||
opcode == SHADER_OPCODE_TXD ||
opcode == SHADER_OPCODE_TXF ||
opcode == SHADER_OPCODE_TXF_MS ||
opcode == SHADER_OPCODE_TXL ||
opcode == SHADER_OPCODE_TXS);
}

7
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
View file

@ -289,6 +289,12 @@ vec4_generator::generate_tex(vec4_instruction *inst,
case SHADER_OPCODE_TXF:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_MS:
if (intel->gen >= 7)
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
else
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXS:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
break;
@ -645,6 +651,7 @@ vec4_generator::generate_vs_instruction(vec4_instruction *instruction,
case SHADER_OPCODE_TEX:
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
generate_tex(inst, dst, src[0]);