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radv,aco: move has_epilog to radv_shader_info

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24404>
This commit is contained in:
Samuel Pitoiset 2023-08-02 08:53:18 +02:00 • committed by Marge Bot
parent eadc72d9de
commit f4ec2e7bb3
10 changed files with 30 additions and 30 deletions
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4
src/amd/compiler/aco_assembler.cpp
View file

@ -1003,7 +1003,7 @@ fix_exports(asm_context& ctx, std::vector<uint32_t>& out, Program* program)
break;
}
} else {
if (!program->info.ps.has_epilog) {
if (!program->info.has_epilog) {
exp.done = true;
exp.valid_mask = true;
}
@ -1016,7 +1016,7 @@ fix_exports(asm_context& ctx, std::vector<uint32_t>& out, Program* program)
/* Do not abort if the main FS has an epilog because it only
* exports MRTZ (if present) and the epilog exports colors.
*/
exported |= program->stage.hw == AC_HW_PIXEL_SHADER && program->info.ps.has_epilog;
exported |= program->stage.hw == AC_HW_PIXEL_SHADER && program->info.has_epilog;
}
++it;
}

29
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -196,12 +196,10 @@ emit_bpermute(isel_context* ctx, Builder& bld, Temp index, Temp data)
* of multiple binaries, because the VGPR use is not known when choosing
* which registers to use for the shared VGPRs.
*/
const bool avoid_shared_vgprs =
ctx->options->gfx_level >= GFX10 && ctx->options->gfx_level < GFX11 &&
ctx->program->wave_size == 64 &&
((ctx->stage == fragment_fs && ctx->program->info.ps.has_epilog) ||
(ctx->stage == tess_control_hs && ctx->program->info.tcs.has_epilog) ||
ctx->stage == raytracing_cs);
const bool avoid_shared_vgprs = ctx->options->gfx_level >= GFX10 &&
ctx->options->gfx_level < GFX11 &&
ctx->program->wave_size == 64 &&
(ctx->program->info.has_epilog || ctx->stage == raytracing_cs);
if (ctx->options->gfx_level <= GFX7 || avoid_shared_vgprs) {
/* GFX6-7: there is no bpermute instruction */
@ -5210,7 +5208,7 @@ store_output_to_temps(isel_context* ctx, nir_intrinsic_instr* instr)
idx++;
}
if (ctx->stage == fragment_fs && ctx->program->info.ps.has_epilog) {
if (ctx->stage == fragment_fs && ctx->program->info.has_epilog) {
unsigned index = nir_intrinsic_base(instr) - FRAG_RESULT_DATA0;
if (nir_intrinsic_src_type(instr) == nir_type_float16) {
@ -11296,14 +11294,17 @@ select_shader(isel_context& ctx, nir_shader* nir, const bool need_startpgm, cons
nir_function_impl* func = nir_shader_get_entrypoint(nir);
visit_cf_list(&ctx, &func->body);
if (ctx.stage == fragment_fs && ctx.program->info.ps.has_epilog) {
create_fs_jump_to_epilog(&ctx);
if (ctx.program->info.has_epilog) {
if (ctx.stage == fragment_fs) {
create_fs_jump_to_epilog(&ctx);
/* FS epilogs always have at least one color/null export. */
ctx.program->has_color_exports = true;
ctx.block->kind |= block_kind_export_end;
} else if (ctx.stage == tess_control_hs && ctx.program->info.tcs.has_epilog) {
create_tcs_jump_to_epilog(&ctx);
/* FS epilogs always have at least one color/null export. */
ctx.program->has_color_exports = true;
ctx.block->kind |= block_kind_export_end;
} else {
assert(ctx.stage == tess_control_hs);
create_tcs_jump_to_epilog(&ctx);
}
}
if (endif_merged_wave_info) {

3
src/amd/compiler/aco_shader_info.h
View file

@ -89,6 +89,7 @@ struct aco_shader_info {
bool has_ngg_early_prim_export;
bool image_2d_view_of_3d;
unsigned workgroup_size;
bool has_epilog; /* Only for TCS or PS. */
struct {
bool tcs_in_out_eq;
uint64_t tcs_temp_only_input_mask;
@ -96,10 +97,8 @@ struct aco_shader_info {
} vs;
struct {
uint32_t num_lds_blocks;
bool has_epilog;
} tcs;
struct {
bool has_epilog;
struct ac_arg epilog_pc;
uint32_t num_interp;
unsigned spi_ps_input;

2
src/amd/vulkan/radv_aco_shader_info.h
View file

@ -48,11 +48,11 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv
ASSIGN_FIELD(has_ngg_culling);
ASSIGN_FIELD(has_ngg_early_prim_export);
ASSIGN_FIELD(workgroup_size);
ASSIGN_FIELD(has_epilog);
ASSIGN_FIELD(vs.tcs_in_out_eq);
ASSIGN_FIELD(vs.tcs_temp_only_input_mask);
ASSIGN_FIELD(vs.has_prolog);
ASSIGN_FIELD(tcs.num_lds_blocks);
ASSIGN_FIELD(ps.has_epilog);
ASSIGN_FIELD(ps.num_interp);
ASSIGN_FIELD(ps.spi_ps_input);
ASSIGN_FIELD(cs.subgroup_size);

4
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -6373,7 +6373,7 @@ radv_bind_fragment_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DB_SHADER_CONTROL;
/* Re-emit the PS epilog when a new fragment shader is bound. */
if (ps->info.ps.has_epilog)
if (ps->info.has_epilog)
cmd_buffer->state.emitted_ps_epilog = NULL;
}
@ -8776,7 +8776,7 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
struct radv_shader_part *ps_epilog = NULL;
if (cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT] &&
cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT]->info.ps.has_epilog) {
cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT]->info.has_epilog) {
if (cmd_buffer->state.ps_epilog) {
ps_epilog = cmd_buffer->state.ps_epilog;
} else if ((cmd_buffer->state.emitted_graphics_pipeline != cmd_buffer->state.graphics_pipeline ||

2
src/amd/vulkan/radv_pipeline.c
View file

@ -670,7 +670,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layo
.enable_mrt_output_nan_fixup =
pipeline_key->ps.epilog.enable_mrt_output_nan_fixup && !stage->nir->info.internal,
.no_color_export = stage->info.ps.has_epilog,
.no_color_export = stage->info.has_epilog,
.bc_optimize_for_persp = G_0286CC_PERSP_CENTER_ENA(stage->info.ps.spi_ps_input) &&
G_0286CC_PERSP_CENTROID_ENA(stage->info.ps.spi_ps_input),

10
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -279,7 +279,7 @@ radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline, const st
return blend;
if (ps) {
if (ps->info.ps.has_epilog) {
if (ps->info.has_epilog) {
spi_shader_col_format = pipeline->ps_epilog->spi_shader_col_format;
} else {
spi_shader_col_format = ps->info.ps.spi_shader_col_format;
@ -2418,7 +2418,7 @@ radv_pipeline_create_ps_epilog(struct radv_device *device, struct radv_graphics_
if (pipeline->base.type == RADV_PIPELINE_GRAPHICS) {
needs_ps_epilog = pipeline->base.shaders[MESA_SHADER_FRAGMENT] &&
pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.has_epilog && !pipeline->ps_epilog;
pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.has_epilog && !pipeline->ps_epilog;
} else {
assert(pipeline->base.type == RADV_PIPELINE_GRAPHICS_LIB);
needs_ps_epilog = (lib_flags & VK_GRAPHICS_PIPELINE_LIBRARY_FRAGMENT_OUTPUT_INTERFACE_BIT_EXT) &&
@ -2471,7 +2471,7 @@ radv_skip_graphics_pipeline_compile(const struct radv_device *device, const stru
/* Do not skip when the PS epilog needs to be compiled. */
if (!radv_pipeline_needs_dynamic_ps_epilog(pipeline) && pipeline->base.shaders[MESA_SHADER_FRAGMENT] &&
pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.has_epilog && !pipeline->ps_epilog)
pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.has_epilog && !pipeline->ps_epilog)
return false;
/* Determine which shader stages have been imported. */
@ -2774,7 +2774,7 @@ radv_pipeline_emit_blend_state(struct radeon_cmdbuf *ctx_cs, const struct radv_g
{
struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
if (ps && ps->info.ps.has_epilog)
if (ps && ps->info.has_epilog)
return;
radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
@ -3938,7 +3938,7 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
pipeline->col_format_non_compacted = blend.spi_shader_col_format;
struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
bool enable_mrt_compaction = ps && !ps->info.ps.has_epilog && !ps->info.ps.mrt0_is_dual_src;
bool enable_mrt_compaction = ps && !ps->info.has_epilog && !ps->info.ps.mrt0_is_dual_src;
if (enable_mrt_compaction) {
blend.spi_shader_col_format = radv_compact_spi_shader_col_format(ps, &blend);

2
src/amd/vulkan/radv_shader.h
View file

@ -306,6 +306,7 @@ struct radv_shader_info {
uint32_t user_data_0;
bool inputs_linked;
bool outputs_linked;
bool has_epilog; /* Only for TCS or PS */
struct {
uint8_t input_usage_mask[RADV_VERT_ATTRIB_MAX];
@ -395,7 +396,6 @@ struct radv_shader_info {
bool allow_flat_shading;
bool pops; /* Uses Primitive Ordered Pixel Shading (fragment shader interlock) */
bool pops_is_per_sample;
bool has_epilog;
bool mrt0_is_dual_src;
unsigned spi_ps_input;
unsigned colors_written;

2
src/amd/vulkan/radv_shader_args.c
View file

@ -672,7 +672,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
case MESA_SHADER_FRAGMENT:
declare_global_input_sgprs(info, user_sgpr_info, args);
if (info->ps.has_epilog) {
if (info->has_epilog) {
add_ud_arg(args, 1, AC_ARG_INT, &args->ps_epilog_pc, AC_UD_PS_EPILOG_PC);
}

2
src/amd/vulkan/radv_shader_info.c
View file

@ -788,7 +788,7 @@ gather_shader_info_fs(const struct radv_device *device, const nir_shader *nir,
info->ps.spi_ps_input = radv_compute_spi_ps_input(pipeline_key, info);
info->ps.has_epilog = pipeline_key->ps.has_epilog && info->ps.colors_written;
info->has_epilog = pipeline_key->ps.has_epilog && info->ps.colors_written;
info->ps.writes_mrt0_alpha = (pipeline_key->ps.alpha_to_coverage_via_mrtz && (info->ps.color0_written & 0x8)) &&
(info->ps.writes_z || info->ps.writes_stencil || info->ps.writes_sample_mask);