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freedreno/ir3: Get reg_size_vec4 from fd_dev_info
Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11790>
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3 changed files with 8 additions and 7 deletions
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@ -57,6 +57,8 @@ struct fd_dev_info {
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/* Information for private memory calculations */
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uint32_t fibers_per_sp;
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uint32_t reg_size_vec4;
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/* Whether the PC_MULTIVIEW_MASK register exists. */
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bool supports_multiview_mask;
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@ -174,12 +174,14 @@ add_gpus([
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# a615, a618, a630:
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a6xx_gen1 = dict(
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fibers_per_sp = 128 * 16,
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reg_size_vec4 = 96,
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ccu_cntl_gmem_unk2 = True,
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)
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# a640, a680:
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a6xx_gen2 = dict(
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fibers_per_sp = 128 * 4 * 16,
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reg_size_vec4 = 96,
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supports_multiview_mask = True,
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has_z24uint_s8uint = True,
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)
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@ -187,6 +189,7 @@ a6xx_gen2 = dict(
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# a650:
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a6xx_gen3 = dict(
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fibers_per_sp = 128 * 2 * 16,
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reg_size_vec4 = 64,
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supports_multiview_mask = True,
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has_z24uint_s8uint = True,
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tess_use_shared = True,
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@ -136,13 +136,9 @@ ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id,
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compiler->max_const_safe = 256;
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}
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if (compiler->gpu_id == 650) {
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/* This changed mid-generation for a650, so that using r32.x and above
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* requires using the smallest threadsize.
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*/
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compiler->reg_size_vec4 = 64;
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} else if (compiler->gpu_id >= 600) {
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compiler->reg_size_vec4 = 96;
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if (compiler->gpu_id >= 600) {
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compiler->reg_size_vec4 =
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fd_dev_info(compiler->gpu_id)->a6xx.reg_size_vec4;
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} else if (compiler->gpu_id >= 400) {
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/* On a4xx-a5xx, using r24.x and above requires using the smallest
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* threadsize.
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