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freedreno/a6xx: Convert to variant reg packers

Browse source 
Convert the builders and drop the -DFD_NO_DEPRECATED_PACK

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37009>
This commit is contained in:
Rob Clark 2025-08-25 11:46:06 -07:00 • committed by Marge Bot
parent b3ac37c515
commit f4ca0093d5
8 changed files with 69 additions and 64 deletions
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2
src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc
View file

@ -322,7 +322,7 @@ emit_blit_setup(fd_ncrb<CHIP> &ncrb, enum pipe_format pfmt,
ncrb.add(A6XX_GRAS_A2D_BLT_CNTL(.dword = blit_cntl));
if (CHIP >= A7XX) {
ncrb.add(A7XX_TPL1_A2D_BLT_CNTL(
ncrb.add(TPL1_A2D_BLT_CNTL(CHIP,
.raw_copy = false,
.start_offset_texels = 0,
.type = A6XX_TEX_2D,

8
src/gallium/drivers/freedreno/a6xx/fd6_compute.cc
View file

@ -52,7 +52,7 @@ cs_program_emit_local_size(struct fd_context *ctx, fd_crb &crb,
.wgtileheight = tile_height,
));
crb.add(A7XX_SP_CS_NDRANGE_7(
crb.add(SP_CS_NDRANGE_7(CHIP,
.localsizex = local_size[0] - 1,
.localsizey = local_size[1] - 1,
.localsizez = local_size[2] - 1,
@ -102,7 +102,7 @@ cs_program_emit(struct fd_context *ctx, fd_crb &crb, struct ir3_shader_variant *
.supports_double_threadsize ? thrsz : THREAD128;
if (CHIP == A6XX) {
crb.add(A6XX_SP_CS_CONST_CONFIG_0(
crb.add(SP_CS_CONST_CONFIG_0(CHIP,
.wgidconstid = work_group_id,
.wgsizeconstid = INVALID_REG,
.wgoffsetconstid = INVALID_REG,
@ -144,7 +144,7 @@ cs_program_emit(struct fd_context *ctx, fd_crb &crb, struct ir3_shader_variant *
v->cs.force_linear_dispatch ? WORKITEMRASTORDER_LINEAR
: WORKITEMRASTORDER_TILED,
));
crb.add(A7XX_SP_CS_UNKNOWN_A9BE(0)); // Sometimes is 0x08000000
crb.add(SP_CS_UNKNOWN_A9BE(CHIP, 0)); // Sometimes is 0x08000000
}
if (!v->local_size_variable)
@ -235,7 +235,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
));
if (CHIP == A6XX && ctx->screen->info->a6xx.has_lpac) {
crb.add(A6XX_HLSQ_CS_CTRL_REG1(
crb.add(HLSQ_CS_CTRL_REG1(CHIP,
.shared_size = shared_size,
.constantrammode = mode,
));

46
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -235,7 +235,7 @@ build_lrz(struct fd6_emit *emit) assert_dt
.z_write_enable = lrz.test,
.z_bounds_enable = lrz.z_bounds_enable,
))
.add(A7XX_GRAS_LRZ_CNTL2(
.add(GRAS_LRZ_CNTL2(CHIP,
.disable_on_wrong_dir = false,
.fc_enable = false,
));
@ -774,7 +774,7 @@ fd6_emit_ccu_cntl(fd_cs &cs, struct fd_screen *screen, bool gmem)
if (CHIP == A7XX) {
fd_pkt4(cs, 1)
.add(A7XX_RB_CCU_CACHE_CNTL(
.add(RB_CCU_CACHE_CNTL(CHIP,
.depth_offset_hi = depth_offset_hi,
.color_offset_hi = color_offset_hi,
.depth_cache_size = CCU_CACHE_SIZE_FULL,
@ -786,9 +786,9 @@ fd6_emit_ccu_cntl(fd_cs &cs, struct fd_screen *screen, bool gmem)
if (screen->info->a7xx.has_gmem_vpc_attr_buf) {
fd_crb(cs, 3)
.add(A7XX_VPC_ATTR_BUF_GMEM_SIZE(.size_gmem = cfg->vpc_attr_buf_size))
.add(A7XX_VPC_ATTR_BUF_GMEM_BASE(.base_gmem = cfg->vpc_attr_buf_offset))
.add(A7XX_PC_ATTR_BUF_GMEM_SIZE(.size_gmem = cfg->vpc_attr_buf_size));
.add(VPC_ATTR_BUF_GMEM_SIZE(CHIP, .size_gmem = cfg->vpc_attr_buf_size))
.add(VPC_ATTR_BUF_GMEM_BASE(CHIP, .base_gmem = cfg->vpc_attr_buf_offset))
.add(PC_ATTR_BUF_GMEM_SIZE(CHIP, .size_gmem = cfg->vpc_attr_buf_size));
}
} else {
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
@ -866,25 +866,25 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs)
ncrb.add(A6XX_SP_DBG_ECO_CNTL(.dword = screen->info->a6xx.magic.SP_DBG_ECO_CNTL));
ncrb.add(A6XX_SP_PERFCTR_SHADER_MASK(.dword = 0x3f));
if (CHIP == A6XX && !screen->info->a6xx.is_a702)
ncrb.add(A6XX_TPL1_UNKNOWN_B605(.dword = 0x44));
ncrb.add(TPL1_UNKNOWN_B605(CHIP, .dword = 0x44));
ncrb.add(A6XX_TPL1_DBG_ECO_CNTL(.dword = screen->info->a6xx.magic.TPL1_DBG_ECO_CNTL));
if (CHIP == A6XX) {
ncrb.add(A6XX_HLSQ_UNKNOWN_BE00(.dword = 0x80));
ncrb.add(A6XX_HLSQ_UNKNOWN_BE01());
ncrb.add(HLSQ_UNKNOWN_BE00(CHIP, .dword = 0x80));
ncrb.add(HLSQ_UNKNOWN_BE01(CHIP));
}
ncrb.add(A6XX_VPC_DBG_ECO_CNTL(.dword = screen->info->a6xx.magic.VPC_DBG_ECO_CNTL));
ncrb.add(A6XX_GRAS_DBG_ECO_CNTL(.dword = screen->info->a6xx.magic.GRAS_DBG_ECO_CNTL));
if (CHIP == A6XX)
ncrb.add(A6XX_HLSQ_DBG_ECO_CNTL(.dword = screen->info->a6xx.magic.HLSQ_DBG_ECO_CNTL));
ncrb.add(HLSQ_DBG_ECO_CNTL(CHIP, .dword = screen->info->a6xx.magic.HLSQ_DBG_ECO_CNTL));
ncrb.add(A6XX_SP_CHICKEN_BITS(.dword = screen->info->a6xx.magic.SP_CHICKEN_BITS));
ncrb.add(A6XX_UCHE_UNKNOWN_0E12(.dword = screen->info->a6xx.magic.UCHE_UNKNOWN_0E12));
ncrb.add(A6XX_UCHE_CLIENT_PF(.dword = screen->info->a6xx.magic.UCHE_CLIENT_PF));
if (CHIP == A6XX) {
ncrb.add(A6XX_HLSQ_SHARED_CONSTS());
ncrb.add(A6XX_VPC_UNKNOWN_9211());
ncrb.add(HLSQ_SHARED_CONSTS(CHIP));
ncrb.add(VPC_UNKNOWN_9211(CHIP));
}
ncrb.add(A6XX_GRAS_UNKNOWN_80AF());
@ -900,8 +900,8 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs)
}
if (screen->info->a7xx.has_hw_bin_scaling) {
ncrb.add(A7XX_GRAS_BIN_FOVEAT());
ncrb.add(A7XX_RB_BIN_FOVEAT());
ncrb.add(GRAS_BIN_FOVEAT(CHIP));
ncrb.add(RB_BIN_FOVEAT(CHIP));
}
}
@ -932,7 +932,15 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs)
);
crb.add(A6XX_VFD_MODE_CNTL(.vertex = true, .instance = true));
crb.add(A6XX_VPC_UNKNOWN_9107());
if (CHIP == A6XX) {
crb.add(VPC_UNKNOWN_9107(CHIP));
} else {
/* This seems to be load-bearing, we need to set it both here
* and below. Previously we were unconditionally zero'ing
* VPC_UNKNOWN_9107 which happens to be the same offset.
*/
crb.add(VPC_RAST_STREAM_CNTL(CHIP));
}
crb.add(A6XX_RB_UNKNOWN_8811(.dword = 0x00000010));
crb.add(A6XX_PC_MODE_CNTL(.dword=screen->info->a6xx.magic.PC_MODE_CNTL));
crb.add(A6XX_GRAS_LRZ_PS_INPUT_CNTL());
@ -958,7 +966,7 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs)
crb.add(VPC_RAST_STREAM_CNTL(CHIP));
if (CHIP == A7XX)
crb.add(A7XX_VPC_RAST_STREAM_CNTL_V2());
crb.add(VPC_RAST_STREAM_CNTL_V2(CHIP));
crb.add(A6XX_PC_STEREO_RENDERING_CNTL());
crb.add(A6XX_SP_UNKNOWN_B183());
@ -967,7 +975,7 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs)
crb.add(A6XX_GRAS_SC_CNTL(.ccusinglecachelinesize = 2));
if (CHIP == A6XX) {
crb.add(A6XX_VPC_UNKNOWN_9210());
crb.add(VPC_UNKNOWN_9210(CHIP));
}
crb.add(A6XX_PC_UNKNOWN_9E72());
@ -991,7 +999,7 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs)
crb.add(A6XX_GRAS_LRZ_CNTL());
if (CHIP >= A7XX)
crb.add(A7XX_GRAS_LRZ_CNTL2());
crb.add(GRAS_LRZ_CNTL2(CHIP));
crb.add(A6XX_RB_LRZ_CNTL());
crb.add(A6XX_RB_DEPTH_PLANE_CNTL());
@ -1013,12 +1021,12 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs)
if (CHIP >= A7XX) {
/* Blob sets these two per draw. */
crb.add(A7XX_PC_HS_BUFFER_SIZE(FD6_TESS_PARAM_SIZE));
crb.add(PC_HS_BUFFER_SIZE(CHIP, FD6_TESS_PARAM_SIZE));
/* Blob adds a bit more space ({0x10, 0x20, 0x30, 0x40} bytes)
* but the meaning of this additional space is not known,
* so we play safe and don't add it.
*/
crb.add(A7XX_PC_TF_BUFFER_SIZE(FD6_TESS_FACTOR_SIZE));
crb.add(PC_TF_BUFFER_SIZE(CHIP, FD6_TESS_FACTOR_SIZE));
}
/* There is an optimization to skip executing draw states for draws with no

32
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -234,7 +234,7 @@ emit_lrz(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *subpass)
crb.add(A6XX_GRAS_LRZ_BUFFER_PITCH());
crb.add(A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE());
if (CHIP >= A7XX)
crb.add(A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO());
crb.add(GRAS_LRZ_DEPTH_BUFFER_INFO(CHIP));
return;
}
@ -260,7 +260,7 @@ emit_lrz(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *subpass)
));
if (CHIP >= A7XX) {
crb.add(A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO(
crb.add(GRAS_LRZ_DEPTH_BUFFER_INFO(CHIP,
.depth_format = fd6_pipe2depth(pfb->zsbuf.format),
));
}
@ -479,7 +479,7 @@ update_render_cntl(fd_cs &cs, struct fd_screen *screen,
.raster_mode = TYPE_TILED,
.raster_direction = LR_TB
));
crb.add(A7XX_GRAS_SU_RENDER_CNTL(
crb.add(GRAS_SU_RENDER_CNTL(CHIP,
.fs_disable = binning,
));
}
@ -1054,12 +1054,12 @@ fd7_emit_static_binning_regs(fd_cs &cs)
{
fd_ncrb<CHIP> ncrb(cs, 6);
ncrb.add(A7XX_RB_UNKNOWN_8812(0x0));
ncrb.add(A7XX_RB_CCU_DBG_ECO_CNTL(0x0));
ncrb.add(A7XX_GRAS_UNKNOWN_8007(0x0));
ncrb.add(RB_UNKNOWN_8812(CHIP, 0x0));
ncrb.add(RB_CCU_DBG_ECO_CNTL(CHIP, 0x0));
ncrb.add(GRAS_UNKNOWN_8007(CHIP, 0x0));
ncrb.add(A6XX_GRAS_UNKNOWN_8110(0x2));
ncrb.add(A7XX_RB_UNKNOWN_8E09(0x4));
ncrb.add(A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_GMEM));
ncrb.add(RB_UNKNOWN_8E09(CHIP, 0x4));
ncrb.add(RB_CLEAR_TARGET(CHIP, .clear_mode = CLEAR_MODE_GMEM));
}
template <chip CHIP>
@ -1436,7 +1436,7 @@ emit_blit(struct fd_batch *batch, fd_crb &crb, uint32_t base,
}
if (CHIP >= A7XX)
crb.add(A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_GMEM));
crb.add(RB_CLEAR_TARGET(CHIP, .clear_mode = CLEAR_MODE_GMEM));
}
template <chip CHIP>
@ -1535,7 +1535,7 @@ emit_subpass_clears(struct fd_batch *batch, fd_cs &cs, struct fd_batch_subpass *
crb.add(A6XX_RB_RESOLVE_CLEAR_COLOR_DW3(uc.ui[3]));
if (CHIP >= A7XX)
crb.add(A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_GMEM));
crb.add(RB_CLEAR_TARGET(CHIP, .clear_mode = CLEAR_MODE_GMEM));
}
fd6_emit_blit<CHIP>(batch->ctx, cs);
@ -1587,7 +1587,7 @@ emit_subpass_clears(struct fd_batch *batch, fd_cs &cs, struct fd_batch_subpass *
crb.add(A6XX_RB_RESOLVE_CLEAR_COLOR_DW0(clear_value));
if (CHIP >= A7XX)
crb.add(A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_GMEM));
crb.add(RB_CLEAR_TARGET(CHIP, .clear_mode = CLEAR_MODE_GMEM));
}
fd6_emit_blit<CHIP>(batch->ctx, cs);
@ -1615,7 +1615,7 @@ emit_subpass_clears(struct fd_batch *batch, fd_cs &cs, struct fd_batch_subpass *
crb.add(A6XX_RB_RESOLVE_CLEAR_COLOR_DW0(subpass->clear_stencil & 0xff));
if (CHIP >= A7XX)
crb.add(A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_GMEM));
crb.add(RB_CLEAR_TARGET(CHIP, .clear_mode = CLEAR_MODE_GMEM));
}
fd6_emit_blit<CHIP>(batch->ctx, cs);
@ -2054,10 +2054,10 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
});
if (CHIP >= A7XX) {
crb.add(A7XX_RB_UNKNOWN_8812(0x3ff)); // all buffers in sysmem
crb.add(A7XX_RB_CCU_DBG_ECO_CNTL(batch->ctx->screen->info->a6xx.magic.RB_CCU_DBG_ECO_CNTL));
crb.add(A7XX_GRAS_UNKNOWN_8007(0x0));
crb.add(A7XX_RB_UNKNOWN_8E09(0x4));
crb.add(RB_UNKNOWN_8812(CHIP, 0x3ff)); // all buffers in sysmem
crb.add(RB_CCU_DBG_ECO_CNTL(CHIP, batch->ctx->screen->info->a6xx.magic.RB_CCU_DBG_ECO_CNTL));
crb.add(GRAS_UNKNOWN_8007(CHIP, 0x0));
crb.add(RB_UNKNOWN_8E09(CHIP, 0x4));
}
/* enable stream-out, with sysmem there is only one pass: */

4
src/gallium/drivers/freedreno/a6xx/fd6_image.cc
View file

@ -278,7 +278,7 @@ fd6_build_bindless_state(struct fd_context *ctx, mesa_shader_stage shader,
));
if (CHIP == A6XX) {
crb.add(A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(
crb.add(HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(CHIP,
idx, .desc_size = BINDLESS_DESCRIPTOR_64B, .bo = set->bo,
));
}
@ -324,7 +324,7 @@ fd6_build_bindless_state(struct fd_context *ctx, mesa_shader_stage shader,
idx, .desc_size = BINDLESS_DESCRIPTOR_64B, .bo = set->bo,
));
if (CHIP == A6XX) {
crb.add(A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(
crb.add(HLSQ_BINDLESS_BASE_DESCRIPTOR(CHIP,
idx, .desc_size = BINDLESS_DESCRIPTOR_64B, .bo = set->bo,
));
}

26
src/gallium/drivers/freedreno/a6xx/fd6_program.cc
View file

@ -89,7 +89,7 @@ emit_shader_regs(struct fd_context *ctx, fd_cs &cs, const struct ir3_shader_vari
));
crb.add(A6XX_SP_VS_PVT_MEM_STACK_OFFSET(.offset = per_sp_size));
if (CHIP >= A7XX)
crb.add(A7XX_SP_VS_VGS_CNTL());
crb.add(SP_VS_VGS_CNTL(CHIP));
break;
case MESA_SHADER_TESS_CTRL:
crb.add(A6XX_SP_HS_CNTL_0(
@ -111,7 +111,7 @@ emit_shader_regs(struct fd_context *ctx, fd_cs &cs, const struct ir3_shader_vari
));
crb.add(A6XX_SP_HS_PVT_MEM_STACK_OFFSET(.offset = per_sp_size));
if (CHIP >= A7XX)
crb.add(A7XX_SP_HS_VGS_CNTL());
crb.add(SP_HS_VGS_CNTL(CHIP));
break;
case MESA_SHADER_TESS_EVAL:
crb.add(A6XX_SP_DS_CNTL_0(
@ -133,7 +133,7 @@ emit_shader_regs(struct fd_context *ctx, fd_cs &cs, const struct ir3_shader_vari
));
crb.add(A6XX_SP_DS_PVT_MEM_STACK_OFFSET(.offset = per_sp_size));
if (CHIP >= A7XX)
crb.add(A7XX_SP_DS_VGS_CNTL());
crb.add(SP_DS_VGS_CNTL(CHIP));
break;
case MESA_SHADER_GEOMETRY:
crb.add(A6XX_SP_GS_CNTL_0(
@ -155,7 +155,7 @@ emit_shader_regs(struct fd_context *ctx, fd_cs &cs, const struct ir3_shader_vari
));
crb.add(A6XX_SP_GS_PVT_MEM_STACK_OFFSET(.offset = per_sp_size));
if (CHIP >= A7XX)
crb.add(A7XX_SP_GS_VGS_CNTL());
crb.add(SP_GS_VGS_CNTL(CHIP));
break;
case MESA_SHADER_FRAGMENT:
crb.add(A6XX_SP_PS_CNTL_0(
@ -183,7 +183,7 @@ emit_shader_regs(struct fd_context *ctx, fd_cs &cs, const struct ir3_shader_vari
));
crb.add(A6XX_SP_PS_PVT_MEM_STACK_OFFSET(.offset = per_sp_size));
if (CHIP >= A7XX)
crb.add(A7XX_SP_PS_VGS_CNTL());
crb.add(SP_PS_VGS_CNTL(CHIP));
break;
case MESA_SHADER_COMPUTE:
thrsz = ctx->screen->info->a6xx.supports_double_threadsize ? thrsz : THREAD128;
@ -208,7 +208,7 @@ emit_shader_regs(struct fd_context *ctx, fd_cs &cs, const struct ir3_shader_vari
));
crb.add(A6XX_SP_CS_PVT_MEM_STACK_OFFSET(.offset = per_sp_size));
if (CHIP >= A7XX)
crb.add(A7XX_SP_CS_VGS_CNTL());
crb.add(SP_CS_VGS_CNTL(CHIP));
break;
default:
UNREACHABLE("bad shader stage");
@ -842,7 +842,7 @@ emit_vpc(fd_crb &crb, const struct program_builder *b)
if (CHIP >= A7XX) {
crb.add(A6XX_GRAS_UNKNOWN_8110(0x2));
crb.add(A7XX_SP_RENDER_CNTL(.fs_disable = false));
crb.add(SP_RENDER_CNTL(CHIP, .fs_disable = false));
}
crb.add(A6XX_VPC_PS_CNTL(
@ -876,17 +876,17 @@ emit_vpc(fd_crb &crb, const struct program_builder *b)
));
if (CHIP >= A7XX) {
crb.add(A7XX_VPC_GS_PARAM_0(
crb.add(VPC_GS_PARAM_0(CHIP,
.gs_vertices_out = vertices_out,
.gs_invocations = invocations,
.gs_output = output,
));
} else {
crb.add(A6XX_VPC_GS_PARAM(0xff));
crb.add(VPC_GS_PARAM(CHIP, 0xff));
}
if (CHIP == A6XX) {
crb.add(A6XX_PC_PRIMITIVE_CNTL_6(vec4_size));
crb.add(PC_PRIMITIVE_CNTL_6(CHIP, vec4_size));
}
uint32_t prim_size = prev_stage_output_size;
@ -1017,7 +1017,7 @@ emit_fs_inputs(fd_crb &crb, const struct program_builder *b)
sysval_regs += 2;
}
crb.add(A7XX_SP_PS_CNTL_1(
crb.add(SP_PS_CNTL_1(CHIP,
.sysval_regs_count = sysval_regs,
.unk8 = 1,
.unk9 = 1,
@ -1137,8 +1137,8 @@ emit_fs_outputs(fd_crb &crb, const struct program_builder *b)
}
if (CHIP >= A7XX) {
crb.add(A7XX_SP_PS_OUTPUT_CONST_CNTL(.enabled = fragdata_aliased_components != 0));
crb.add(A7XX_SP_PS_OUTPUT_CONST_MASK(.dword = fragdata_aliased_components));
crb.add(SP_PS_OUTPUT_CONST_CNTL(CHIP, .enabled = fragdata_aliased_components != 0));
crb.add(SP_PS_OUTPUT_CONST_MASK(CHIP, .dword = fragdata_aliased_components));
} else {
assert(fragdata_aliased_components == 0);
}

12
src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.cc
View file

@ -71,7 +71,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
);
if (CHIP >= A7XX) {
crb.add(A7XX_VPC_PC_CNTL(
crb.add(VPC_PC_CNTL(CHIP,
.primitive_restart = primitive_restart,
.provoking_vtx_last = !cso->flatshade_first,
)
@ -96,7 +96,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
if (CHIP == A7XX ||
(CHIP == A6XX && ctx->screen->info->a6xx.is_a702)) {
crb.add(A6XX_VPC_PS_RAST_CNTL(mode));
crb.add(VPC_PS_RAST_CNTL(CHIP, mode));
}
/* With a7xx the hw doesn't do the clamping for us. When depth clamp
@ -120,10 +120,10 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
}
if (CHIP == A6XX && ctx->screen->info->a6xx.has_legacy_pipeline_shading_rate) {
crb.add(A6XX_RB_UNKNOWN_8A00());
crb.add(A6XX_RB_UNKNOWN_8A10());
crb.add(A6XX_RB_UNKNOWN_8A20());
crb.add(A6XX_RB_UNKNOWN_8A30());
crb.add(RB_UNKNOWN_8A00(CHIP));
crb.add(RB_UNKNOWN_8A10(CHIP));
crb.add(RB_UNKNOWN_8A20(CHIP));
crb.add(RB_UNKNOWN_8A30(CHIP));
}
return crb.ring();

3
src/gallium/drivers/freedreno/meson.build
View file

@ -252,9 +252,6 @@ freedreno_cpp_args += cpp.get_supported_arguments([
'-Wno-vla-cxx-extension',
])
# Temporarily quiet deprecated warnings until gallium driver is converted:
freedreno_cpp_args += '-DFD_NO_DEPRECATED_PACK'
libfreedreno_dependencies = [
dep_libdrm,
idep_mesautil,