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i965: Consolidate BRW_NEW_TESS_{CTRL,EVAL}_PROGRAM flags.

Browse source 
For several reasons, I don't think it's particularly useful to have
separate flags:

1. Most of the time, tessellation shaders are paired, so both will be
   replaced at the same time.

2. The data layout is tightly coupled.  Both need to agree on the number
   of per-patch slots in the VUE map.  Even adding extra TCS outputs
   that aren't read by the TES will trigger the need for recompiles.

3. The TCS is optional from an API perspective, but required by the
   hardware whenever tessellation is enabled.  So, atoms that deal with
   the TCS must check brw->tess_eval_program (BRW_NEW_TESS_EVAL_PROGRAM?)
   rather than brw->tess_ctrl_program to tell whether tessellation is
   enabled.

So, not only is it unlikely to be useful, it's a bit confusing to get
right.  Simply using one flag for both simplifies this.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Kenneth Graunke 2015-12-17 21:02:40 -08:00
parent 8498cb4a45
commit f46dbfaed9
14 changed files with 37 additions and 47 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -179,8 +179,7 @@ enum brw_state_id {
BRW_STATE_URB_FENCE = BRW_MAX_CACHE,
BRW_STATE_FRAGMENT_PROGRAM,
BRW_STATE_GEOMETRY_PROGRAM,
BRW_STATE_TESS_CTRL_PROGRAM,
BRW_STATE_TESS_EVAL_PROGRAM,
BRW_STATE_TESS_PROGRAMS,
BRW_STATE_VERTEX_PROGRAM,
BRW_STATE_CURBE_OFFSETS,
BRW_STATE_REDUCED_PRIMITIVE,
@ -262,8 +261,7 @@ enum brw_state_id {
#define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
#define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
#define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
#define BRW_NEW_TESS_EVAL_PROGRAM (1ull << BRW_STATE_TESS_EVAL_PROGRAM)
#define BRW_NEW_TESS_CTRL_PROGRAM (1ull << BRW_STATE_TESS_CTRL_PROGRAM)
#define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
#define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
#define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
#define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)

8
src/mesa/drivers/dri/i965/brw_sampler_state.c
View file

@ -654,7 +654,7 @@ const struct brw_tracked_state brw_gs_samplers = {
static void
brw_upload_tcs_samplers(struct brw_context *brw)
{
/* BRW_NEW_TESS_CTRL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
struct gl_program *tcs = (struct gl_program *) brw->tess_ctrl_program;
if (!tcs)
return;
@ -667,7 +667,7 @@ const struct brw_tracked_state brw_tcs_samplers = {
.dirty = {
.mesa = _NEW_TEXTURE,
.brw = BRW_NEW_BATCH |
BRW_NEW_TESS_CTRL_PROGRAM,
BRW_NEW_TESS_PROGRAMS,
},
.emit = brw_upload_tcs_samplers,
};
@ -676,7 +676,7 @@ const struct brw_tracked_state brw_tcs_samplers = {
static void
brw_upload_tes_samplers(struct brw_context *brw)
{
/* BRW_NEW_TESS_EVAL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
struct gl_program *tes = (struct gl_program *) brw->tess_eval_program;
if (!tes)
return;
@ -689,7 +689,7 @@ const struct brw_tracked_state brw_tes_samplers = {
.dirty = {
.mesa = _NEW_TEXTURE,
.brw = BRW_NEW_BATCH |
BRW_NEW_TESS_EVAL_PROGRAM,
BRW_NEW_TESS_PROGRAMS,
},
.emit = brw_upload_tes_samplers,
};

7
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -607,8 +607,7 @@ static struct dirty_bit_map brw_bits[] = {
DEFINE_BIT(BRW_NEW_URB_FENCE),
DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM),
DEFINE_BIT(BRW_NEW_TESS_EVAL_PROGRAM),
DEFINE_BIT(BRW_NEW_TESS_CTRL_PROGRAM),
DEFINE_BIT(BRW_NEW_TESS_PROGRAMS),
DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
@ -761,12 +760,12 @@ brw_upload_pipeline_state(struct brw_context *brw,
if (brw->tess_eval_program != ctx->TessEvalProgram._Current) {
brw->tess_eval_program = ctx->TessEvalProgram._Current;
brw->ctx.NewDriverState |= BRW_NEW_TESS_EVAL_PROGRAM;
brw->ctx.NewDriverState |= BRW_NEW_TESS_PROGRAMS;
}
if (brw->tess_ctrl_program != ctx->TessCtrlProgram._Current) {
brw->tess_ctrl_program = ctx->TessCtrlProgram._Current;
brw->ctx.NewDriverState |= BRW_NEW_TESS_CTRL_PROGRAM;
brw->ctx.NewDriverState |= BRW_NEW_TESS_PROGRAMS;
}
if (brw->geometry_program != ctx->GeometryProgram._Current) {

6
src/mesa/drivers/dri/i965/brw_tcs.c
View file

@ -184,10 +184,9 @@ brw_upload_tcs_prog(struct brw_context *brw)
struct gl_shader_program **current = ctx->_Shader->CurrentProgram;
struct brw_stage_state *stage_state = &brw->tcs.base;
struct brw_tcs_prog_key key;
/* BRW_NEW_TESS_CTRL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
struct brw_tess_ctrl_program *tcp =
(struct brw_tess_ctrl_program *) brw->tess_ctrl_program;
/* BRW_NEW_TESS_EVAL_PROGRAM */
struct brw_tess_eval_program *tep =
(struct brw_tess_eval_program *) brw->tess_eval_program;
assert(tcp && tep);
@ -195,8 +194,7 @@ brw_upload_tcs_prog(struct brw_context *brw)
if (!brw_state_dirty(brw,
_NEW_TEXTURE,
BRW_NEW_PATCH_PRIMITIVE |
BRW_NEW_TESS_CTRL_PROGRAM |
BRW_NEW_TESS_EVAL_PROGRAM))
BRW_NEW_TESS_PROGRAMS))
return;
struct gl_program *prog = &tcp->program.Base;

8
src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
View file

@ -39,7 +39,7 @@ brw_upload_tcs_pull_constants(struct brw_context *brw)
{
struct brw_stage_state *stage_state = &brw->tcs.base;
/* BRW_NEW_TESS_CTRL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
struct brw_tess_ctrl_program *tcp =
(struct brw_tess_ctrl_program *) brw->tess_ctrl_program;
@ -59,7 +59,7 @@ const struct brw_tracked_state brw_tcs_pull_constants = {
.mesa = _NEW_PROGRAM_CONSTANTS,
.brw = BRW_NEW_BATCH |
BRW_NEW_TCS_PROG_DATA |
BRW_NEW_TESS_CTRL_PROGRAM,
BRW_NEW_TESS_PROGRAMS,
},
.emit = brw_upload_tcs_pull_constants,
};
@ -122,7 +122,7 @@ static void
brw_upload_tcs_image_surfaces(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_TESS_CTRL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
struct gl_shader_program *prog =
ctx->_Shader->CurrentProgram[MESA_SHADER_TESS_CTRL];
@ -138,7 +138,7 @@ const struct brw_tracked_state brw_tcs_image_surfaces = {
.brw = BRW_NEW_BATCH |
BRW_NEW_TCS_PROG_DATA |
BRW_NEW_IMAGE_UNITS |
BRW_NEW_TESS_CTRL_PROGRAM,
BRW_NEW_TESS_PROGRAMS,
},
.emit = brw_upload_tcs_image_surfaces,
};

4
src/mesa/drivers/dri/i965/brw_tes.c
View file

@ -232,13 +232,13 @@ brw_upload_tes_prog(struct brw_context *brw)
struct gl_shader_program **current = ctx->_Shader->CurrentProgram;
struct brw_stage_state *stage_state = &brw->tes.base;
struct brw_tes_prog_key key;
/* BRW_NEW_TESS_EVAL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
struct brw_tess_eval_program *tep =
(struct brw_tess_eval_program *) brw->tess_eval_program;
if (!brw_state_dirty(brw,
_NEW_TEXTURE,
BRW_NEW_TESS_EVAL_PROGRAM))
BRW_NEW_TESS_PROGRAMS))
return;
struct gl_program *prog = &tep->program.Base;

8
src/mesa/drivers/dri/i965/brw_tes_surface_state.c
View file

@ -39,7 +39,7 @@ brw_upload_tes_pull_constants(struct brw_context *brw)
{
struct brw_stage_state *stage_state = &brw->tes.base;
/* BRW_NEW_TESS_EVAL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
struct brw_tess_eval_program *dp =
(struct brw_tess_eval_program *) brw->tess_eval_program;
@ -59,7 +59,7 @@ const struct brw_tracked_state brw_tes_pull_constants = {
.mesa = _NEW_PROGRAM_CONSTANTS,
.brw = BRW_NEW_BATCH |
BRW_NEW_TES_PROG_DATA |
BRW_NEW_TESS_EVAL_PROGRAM,
BRW_NEW_TESS_PROGRAMS,
},
.emit = brw_upload_tes_pull_constants,
};
@ -122,7 +122,7 @@ static void
brw_upload_tes_image_surfaces(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_TESS_EVAL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
struct gl_shader_program *prog =
ctx->_Shader->CurrentProgram[MESA_SHADER_TESS_EVAL];
@ -137,7 +137,7 @@ const struct brw_tracked_state brw_tes_image_surfaces = {
.dirty = {
.brw = BRW_NEW_BATCH |
BRW_NEW_IMAGE_UNITS |
BRW_NEW_TESS_EVAL_PROGRAM |
BRW_NEW_TESS_PROGRAMS |
BRW_NEW_TES_PROG_DATA,
},
.emit = brw_upload_tes_image_surfaces,

7
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View file

@ -862,10 +862,8 @@ brw_update_texture_surfaces(struct brw_context *brw)
/* BRW_NEW_VERTEX_PROGRAM */
struct gl_program *vs = (struct gl_program *) brw->vertex_program;
/* BRW_NEW_TESS_CTRL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
struct gl_program *tcs = (struct gl_program *) brw->tess_ctrl_program;
/* BRW_NEW_TESS_EVAL_PROGRAM */
struct gl_program *tes = (struct gl_program *) brw->tess_eval_program;
/* BRW_NEW_GEOMETRY_PROGRAM */
@ -915,8 +913,7 @@ const struct brw_tracked_state brw_texture_surfaces = {
BRW_NEW_FS_PROG_DATA |
BRW_NEW_GEOMETRY_PROGRAM |
BRW_NEW_GS_PROG_DATA |
BRW_NEW_TESS_CTRL_PROGRAM |
BRW_NEW_TESS_EVAL_PROGRAM |
BRW_NEW_TESS_PROGRAMS |
BRW_NEW_TCS_PROG_DATA |
BRW_NEW_TES_PROG_DATA |
BRW_NEW_TEXTURE_BUFFER |

4
src/mesa/drivers/dri/i965/gen7_ds_state.c
View file

@ -30,7 +30,7 @@ static void
gen7_upload_tes_push_constants(struct brw_context *brw)
{
struct brw_stage_state *stage_state = &brw->tes.base;
/* BRW_NEW_TESS_EVAL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
const struct brw_tess_eval_program *tep =
(struct brw_tess_eval_program *) brw->tess_eval_program;
@ -49,7 +49,7 @@ const struct brw_tracked_state gen7_tes_push_constants = {
.mesa = _NEW_PROGRAM_CONSTANTS,
.brw = BRW_NEW_BATCH |
BRW_NEW_PUSH_CONSTANT_ALLOCATION |
BRW_NEW_TESS_EVAL_PROGRAM |
BRW_NEW_TESS_PROGRAMS |
BRW_NEW_TES_PROG_DATA,
},
.emit = gen7_upload_tes_push_constants,

4
src/mesa/drivers/dri/i965/gen7_hs_state.c
View file

@ -30,7 +30,7 @@ static void
gen7_upload_tcs_push_constants(struct brw_context *brw)
{
struct brw_stage_state *stage_state = &brw->tcs.base;
/* BRW_NEW_TESS_CTRL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
const struct brw_tess_ctrl_program *tcp =
(struct brw_tess_ctrl_program *) brw->tess_ctrl_program;
@ -49,7 +49,7 @@ const struct brw_tracked_state gen7_tcs_push_constants = {
.mesa = _NEW_PROGRAM_CONSTANTS,
.brw = BRW_NEW_BATCH |
BRW_NEW_PUSH_CONSTANT_ALLOCATION |
BRW_NEW_TESS_CTRL_PROGRAM |
BRW_NEW_TESS_PROGRAMS |
BRW_NEW_TCS_PROG_DATA,
},
.emit = gen7_upload_tcs_push_constants,

4
src/mesa/drivers/dri/i965/gen7_te_state.c
View file

@ -29,7 +29,7 @@
static void
upload_te_state(struct brw_context *brw)
{
/* BRW_NEW_TESS_EVAL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
bool active = brw->tess_eval_program;
if (active)
assert(brw->tess_ctrl_program);
@ -61,7 +61,7 @@ const struct brw_tracked_state gen7_te_state = {
.mesa = 0,
.brw = BRW_NEW_CONTEXT |
BRW_NEW_TES_PROG_DATA |
BRW_NEW_TESS_EVAL_PROGRAM,
BRW_NEW_TESS_PROGRAMS,
},
.emit = upload_te_state,
};

10
src/mesa/drivers/dri/i965/gen7_urb.c
View file

@ -63,7 +63,7 @@ gen7_allocate_push_constants(struct brw_context *brw)
/* BRW_NEW_GEOMETRY_PROGRAM */
bool gs_present = brw->geometry_program;
/* BRW_NEW_TESS_CTRL_PROGRAM, BRW_NEW_TESS_EVAL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
bool tess_present = brw->tess_eval_program;
unsigned avail_size = 16;
@ -146,8 +146,7 @@ const struct brw_tracked_state gen7_push_constant_space = {
.mesa = 0,
.brw = BRW_NEW_CONTEXT |
BRW_NEW_GEOMETRY_PROGRAM |
BRW_NEW_TESS_CTRL_PROGRAM |
BRW_NEW_TESS_EVAL_PROGRAM,
BRW_NEW_TESS_PROGRAMS,
},
.emit = gen7_allocate_push_constants,
};
@ -167,7 +166,7 @@ gen7_upload_urb(struct brw_context *brw)
unsigned gs_size = gs_present ? brw->gs.prog_data->base.urb_entry_size : 1;
unsigned gs_entry_size_bytes = gs_size * 64;
/* BRW_NEW_TESS_CTRL_PROGRAM, BRW_NEW_TESS_EVAL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
const bool tess_present = brw->tess_eval_program;
assert(!tess_present || brw->tess_ctrl_program);
/* BRW_NEW_TCS_PROG_DATA */
@ -422,8 +421,7 @@ const struct brw_tracked_state gen7_urb = {
.brw = BRW_NEW_CONTEXT |
BRW_NEW_URB_SIZE |
BRW_NEW_GEOMETRY_PROGRAM |
BRW_NEW_TESS_CTRL_PROGRAM |
BRW_NEW_TESS_EVAL_PROGRAM |
BRW_NEW_TESS_PROGRAMS |
BRW_NEW_GS_PROG_DATA |
BRW_NEW_TCS_PROG_DATA |
BRW_NEW_TES_PROG_DATA |

4
src/mesa/drivers/dri/i965/gen8_ds_state.c
View file

@ -31,7 +31,7 @@ gen8_upload_ds_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
const struct brw_stage_state *stage_state = &brw->tes.base;
/* BRW_NEW_TESS_EVAL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
bool active = brw->tess_eval_program;
assert(!active || brw->tess_ctrl_program);
@ -92,7 +92,7 @@ const struct brw_tracked_state gen8_ds_state = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_TESS_EVAL_PROGRAM |
BRW_NEW_TESS_PROGRAMS |
BRW_NEW_TES_PROG_DATA,
},
.emit = gen8_upload_ds_state,

4
src/mesa/drivers/dri/i965/gen8_hs_state.c
View file

@ -30,7 +30,7 @@ static void
gen8_upload_hs_state(struct brw_context *brw)
{
const struct brw_stage_state *stage_state = &brw->tcs.base;
/* BRW_NEW_TESS_CTRL_PROGRAM */
/* BRW_NEW_TESS_PROGRAMS */
bool active = brw->tess_ctrl_program;
assert(!active || brw->tess_eval_program);
/* BRW_NEW_HS_PROG_DATA */
@ -84,7 +84,7 @@ const struct brw_tracked_state gen8_hs_state = {
.mesa = 0,
.brw = BRW_NEW_BATCH |
BRW_NEW_TCS_PROG_DATA |
BRW_NEW_TESS_CTRL_PROGRAM,
BRW_NEW_TESS_PROGRAMS,
},
.emit = gen8_upload_hs_state,
};