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nir,ac/llvm,aco: remove nir_export_primitive_amd

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Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
This commit is contained in:
Qiang Yu 2022-12-25 22:41:39 +08:00 • committed by Marge Bot
parent aea109e25d
commit f44872c7b6
3 changed files with 0 additions and 65 deletions
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57
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -8178,7 +8178,6 @@ emit_interp_center(isel_context* ctx, Temp dst, Temp bary, Temp pos1, Temp pos2)
Temp merged_wave_info_to_mask(isel_context* ctx, unsigned i);
Temp lanecount_to_mask(isel_context* ctx, Temp count);
void ngg_emit_sendmsg_gs_alloc_req(isel_context* ctx, Temp vtx_cnt, Temp prm_cnt);
static void create_primitive_exports(isel_context *ctx, Temp prim_ch1);
static void create_vs_exports(isel_context* ctx);
Temp
@ -9080,11 +9079,6 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
create_vs_exports(ctx);
break;
}
case nir_intrinsic_export_primitive_amd: {
Temp prim_ch1 = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
create_primitive_exports(ctx, prim_ch1);
break;
}
case nir_intrinsic_alloc_vertices_and_primitives_amd: {
assert(ctx->stage.hw == HWStage::NGG);
Temp num_vertices = get_ssa_temp(ctx, instr->src[0].ssa);
@ -10962,57 +10956,6 @@ create_vs_exports(isel_context* ctx)
}
}
static void
create_primitive_exports(isel_context *ctx, Temp prim_ch1)
{
assert(ctx->stage.hw == HWStage::NGG);
const aco_vp_output_info* outinfo = &ctx->program->info.outinfo;
Builder bld(ctx->program, ctx->block);
/* When layer, viewport etc. are per-primitive, they need to be encoded in
* the primitive export instruction's second channel. The encoding is:
* bits 31..30: VRS rate Y
* bits 29..28: VRS rate X
* bits 23..20: viewport
* bits 19..17: layer
*/
Temp ch2 = bld.copy(bld.def(v1), Operand::c32(0));
unsigned en_mask = 1;
if (outinfo->writes_layer_per_primitive) {
en_mask |= 2;
Temp tmp = ctx->outputs.temps[VARYING_SLOT_LAYER * 4u];
ch2 = bld.vop3(aco_opcode::v_lshl_or_b32, bld.def(v1), tmp, Operand::c32(17), ch2);
}
if (outinfo->writes_viewport_index_per_primitive) {
en_mask |= 2;
Temp tmp = ctx->outputs.temps[VARYING_SLOT_VIEWPORT * 4u];
ch2 = bld.vop3(aco_opcode::v_lshl_or_b32, bld.def(v1), tmp, Operand::c32(20), ch2);
}
if (outinfo->writes_primitive_shading_rate_per_primitive) {
en_mask |= 2;
Temp tmp = ctx->outputs.temps[VARYING_SLOT_PRIMITIVE_SHADING_RATE * 4u];
ch2 = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), tmp, ch2);
}
Operand prim_ch2 = (en_mask & 2) ? Operand(ch2) : Operand(v1);
bld.exp(aco_opcode::exp, prim_ch1, prim_ch2, Operand(v1), Operand(v1),
en_mask /* enabled mask */, V_008DFC_SQ_EXP_PRIM /* dest */, false /* compressed */,
true /* done */, false /* valid mask */);
/* Export generic per-primitive attributes. */
for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
if (!(ctx->shader->info.per_primitive_outputs & BITFIELD64_BIT(i)))
continue;
if (i == VARYING_SLOT_PRIMITIVE_SHADING_RATE)
continue;
export_vs_varying(ctx, i, false, NULL);
}
}
static bool
export_fs_mrt_z(isel_context* ctx)
{

6
src/amd/llvm/ac_nir_to_llvm.c
View file

@ -4138,12 +4138,6 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
ctx->abi->tes_rel_patch_id_replaced = get_src(ctx, instr->src[3]);
ctx->abi->tes_patch_id_replaced = get_src(ctx, instr->src[2]);
break;
case nir_intrinsic_export_primitive_amd: {
struct ac_ngg_prim prim = {0};
prim.passthrough = get_src(ctx, instr->src[0]);
ac_build_export_prim(&ctx->ac, &prim);
break;
}
case nir_intrinsic_gds_atomic_add_amd: {
LLVMValueRef store_val = get_src(ctx, instr->src[0]);
LLVMValueRef addr = get_src(ctx, instr->src[1]);

2
src/compiler/nir/nir_intrinsics.py
View file

@ -1425,8 +1425,6 @@ intrinsic("load_cull_small_prim_precision_amd", dest_comp=1, bit_sizes=[32], fla
intrinsic("load_initial_edgeflags_amd", src_comp=[], dest_comp=1, bit_sizes=[32], indices=[])
# Exports the current invocation's vertex. This is a placeholder where all vertex attribute export instructions should be emitted.
intrinsic("export_vertex_amd", src_comp=[], indices=[])
# Exports the current invocation's primitive. src[] = {packed_primitive_data}.
intrinsic("export_primitive_amd", src_comp=[1], indices=[])
# Allocates export space for vertices and primitives. src[] = {num_vertices, num_primitives}.
intrinsic("alloc_vertices_and_primitives_amd", src_comp=[1, 1], indices=[])
# Overwrites VS input registers, for use with vertex compaction after culling. src = {vertex_id, instance_id}.