From f42d52f9224ca48f7e0b45bb85f14aa0f4ddd4ea Mon Sep 17 00:00:00 2001 From: Konstantin Seurer Date: Mon, 12 May 2025 21:05:55 +0200 Subject: [PATCH] radv: Flush L2 on GFX12 when binding an update pipeline This is just for completeness since the flush above is probably sufficient. Fixes: 2d48b2c ("radv: Use subgroup OPs for BVH updates on GFX12") Reviewed-by: Natalie Vock Part-of: --- src/amd/vulkan/radv_acceleration_structure.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/amd/vulkan/radv_acceleration_structure.c b/src/amd/vulkan/radv_acceleration_structure.c index ce32880f657..9cc7f0edc9b 100644 --- a/src/amd/vulkan/radv_acceleration_structure.c +++ b/src/amd/vulkan/radv_acceleration_structure.c @@ -743,6 +743,9 @@ radv_update_bind_pipeline(VkCommandBuffer commandBuffer, uint32_t key) radv_dst_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, VK_ACCESS_2_SHADER_READ_BIT, 0, NULL, NULL); + if (radv_device_physical(device)->info.cp_sdma_ge_use_system_memory_scope) + cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_L2; + bool in_place = key & RADV_BUILD_FLAG_UPDATE_IN_PLACE; uint32_t flags = in_place ? RADV_BUILD_FLAG_UPDATE_IN_PLACE : 0;