From f421eecebe4c01fa69c0c0cfea23905b68b5e8cd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
Date: Sat, 14 Feb 2026 04:03:41 -0500
Subject: [PATCH] radv,radeonsi: PA_SC_BINNER changes for gfx12
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Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40022>
---
 docs/drivers/amd/hw/pops.rst                    |  3 ++-
 src/amd/vulkan/radv_cmd_buffer.c                | 15 +++++++++++++++
 src/gallium/drivers/radeonsi/si_state_binning.c | 15 +++++++++++++++
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/docs/drivers/amd/hw/pops.rst b/docs/drivers/amd/hw/pops.rst
index 5941c0ff08e..e9dccb0b53e 100644
--- a/docs/drivers/amd/hw/pops.rst
+++ b/docs/drivers/amd/hw/pops.rst
@@ -473,4 +473,5 @@ No effect was found in `nvpro-samples/vk_order_independent_transparency <https:/
 during testing on GFX9 ``CHIP_RAVEN`` and GFX11 ``CHIP_NAVI31``.
 
 * ``DB_SHADER_CONTROL.EXEC_IF_OVERLAPPED`` on GFX9–10.3.
-* ``PA_SC_BINNER_CNTL_0.BIN_MAPPING_MODE = BIN_MAP_MODE_POPS`` on GFX10+.
+* ``PA_SC_BINNER_CNTL_0.BIN_MAPPING_MODE = BIN_MAP_MODE_POPS`` on GFX10-11.5.
+  This field is reserved on GFX12+ and should be set to 0.
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 797de66b537..3331dc7b730 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2276,6 +2276,16 @@ radv_gfx10_compute_bin_size(struct radv_cmd_buffer *cmd_buffer)
    extent.width = MAX2(extent.width, 128);
    extent.height = MAX2(extent.width, pdev->info.gfx_level >= GFX12 ? 128 : 64);
 
+   if (pdev->info.gfx_level >= GFX12) {
+      /* GFX12+ notes:
+       * - The minimum size is 128x128 for greater than 16K framebuffers.
+       *   (GFX12 always requires at least 128 regardless of the size)
+       * - BIN_SIZE_X and BIN_SIZE_Y must be 0 and are unsupported.
+       */
+      extent.width = MAX2(extent.width, 128);
+      extent.height = MAX2(extent.height, 128);
+   }
+
    return extent;
 }
 
@@ -2556,6 +2566,11 @@ radv_get_disabled_binning_state(struct radv_cmd_buffer *cmd_buffer)
    uint32_t pa_sc_binner_cntl_0;
 
    if (pdev->info.gfx_level >= GFX12) {
+      /* GFX12+ notes:
+       * - The minimum size is 128x128 for greater than 16K framebuffers.
+       *   (GFX12 always requires at least 128 regardless of the size)
+       * - BIN_SIZE_X and BIN_SIZE_Y must be 0 and are unsupported.
+       */
       const uint32_t bin_size_x = 128, bin_size_y = 128;
 
       pa_sc_binner_cntl_0 =
diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index a6557a00eee..b6f8a6c7a0e 100644
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -391,6 +391,11 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
    radeon_begin(&sctx->gfx_cs);
 
    if (sctx->gfx_level >= GFX12) {
+      /* GFX12+ notes:
+       * - The minimum size is 128x128 for greater than 16K framebuffers.
+       *   (GFX12 always requires at least 128 regardless of the size)
+       * - BIN_SIZE_X and BIN_SIZE_Y must be 0 and are unsupported.
+       */
       struct uvec2 bin_size = {128, 128};
 
       radeon_opt_set_context_reg(R_028C44_PA_SC_BINNER_CNTL_0,
@@ -511,6 +516,16 @@ void si_emit_dpbb_state(struct si_context *sctx, unsigned index)
    if (bin_size.y >= 32)
       bin_size_extend.y = util_logbase2(bin_size.y) - 5;
 
+   if (sctx->gfx_level >= GFX12) {
+      /* GFX12+ notes:
+       * - The minimum size is 128x128 for greater than 16K framebuffers.
+       *   (GFX12 always requires at least 128 regardless of the size)
+       * - BIN_SIZE_X and BIN_SIZE_Y must be 0 and are unsupported.
+       */
+      bin_size.x = MAX2(bin_size.x, 128);
+      bin_size.y = MAX2(bin_size.y, 128);
+   }
+
    radeon_begin(&sctx->gfx_cs);
    radeon_opt_set_context_reg(R_028C44_PA_SC_BINNER_CNTL_0, AC_TRACKED_PA_SC_BINNER_CNTL_0,
                               S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |