diff --git a/src/mesa/drivers/dri/i915/i830_metaops.c b/src/mesa/drivers/dri/i915/i830_metaops.c
index a2a9baf7d75..9a1933b8dba 100644
--- a/src/mesa/drivers/dri/i915/i830_metaops.c
+++ b/src/mesa/drivers/dri/i915/i830_metaops.c
@@ -42,10 +42,10 @@
 /* A large amount of state doesn't need to be uploaded.
  */
 #define ACTIVE (I830_UPLOAD_INVARIENT |         \
-		I830_UPLOAD_TEXBLEND(0) |	\
-		I830_UPLOAD_STIPPLE |		\
 		I830_UPLOAD_CTX |		\
 		I830_UPLOAD_BUFFERS |		\
+		I830_UPLOAD_STIPPLE |		\
+		I830_UPLOAD_TEXBLEND(0) |	\
 		I830_UPLOAD_TEX(0))		
 
 
@@ -184,8 +184,8 @@ static void set_texture_blend_replace( struct intel_context *intel )
    struct i830_context *i830 = i830_context(&intel->ctx);
    static const struct gl_tex_env_combine_state comb = {
       GL_REPLACE, GL_REPLACE,
-      { GL_TEXTURE, 0, 0, }, { GL_TEXTURE, 0, 0, },
-      { GL_SRC_COLOR, 0, 0 }, { GL_SRC_ALPHA, 0, 0 },
+      { GL_TEXTURE, GL_TEXTURE, GL_TEXTURE, }, { GL_TEXTURE, GL_TEXTURE, GL_TEXTURE, },
+      { GL_SRC_COLOR, GL_SRC_COLOR, GL_SRC_COLOR }, { GL_SRC_ALPHA, GL_SRC_ALPHA, GL_SRC_ALPHA },
       0, 0, 1, 1
    };
 
@@ -272,16 +272,23 @@ static GLboolean set_tex_rect_source( struct intel_context *intel,
       return GL_FALSE;
    }
 
+   i830->meta.tex_buffer[0] = buffer;
+   i830->meta.tex_offset[0] = offset;
 
    setup[I830_TEXREG_TM0LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_2 | 
 			       (LOAD_TEXTURE_MAP0 << 0) | 4);
    setup[I830_TEXREG_TM0S1] = (((height - 1) << TM0S1_HEIGHT_SHIFT) |
 			       ((pitch - 1) << TM0S1_WIDTH_SHIFT) |
 			       textureFormat);
-   setup[I830_TEXREG_TM0S2] = (((((pitch * cpp) / 4) - 1) << TM0S2_PITCH_SHIFT));   
-   setup[I830_TEXREG_TM0S3] &= ~TM0S3_MAX_MIP_MASK;
-   setup[I830_TEXREG_TM0S3] &= ~TM0S3_MIN_MIP_MASK;
-   setup[I830_TEXREG_TM0S3] |= ((numLevels - 1)*4) << TM0S3_MIN_MIP_SHIFT;
+   setup[I830_TEXREG_TM0S2] = (((((pitch * cpp) / 4) - 1) << TM0S2_PITCH_SHIFT)  |
+			       TM0S2_CUBE_FACE_ENA_MASK);   
+
+   setup[I830_TEXREG_TM0S3] = ( (((numLevels - 1)*4) << TM0S3_MIN_MIP_SHIFT) |
+				(FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT) |
+				(MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT) |
+				(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT));
+
+   setup[I830_TEXREG_CUBE] = (_3DSTATE_MAP_CUBE | MAP_UNIT(0));
 
    setup[I830_TEXREG_MCS] = (_3DSTATE_MAP_COORD_SET_CMD |
 			     MAP_UNIT(0) |
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index f6c5b5bf346..e2f7e6ba4b2 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -344,11 +344,13 @@ static void i830_emit_invarient_state( struct intel_context *intel )
 #define emit( intel, state, size )			\
 do {							\
    int k;						\
-   BEGIN_BATCH(size / sizeof(GLuint), 0);			\
-   for (k = 0 ; k < size / sizeof(GLuint) ; k++)	\
+   BEGIN_BATCH(size / sizeof(GLuint), 0);		\
+   for (k = 0 ; k < size / sizeof(GLuint) ; k++) {	\
+      if (0) _mesa_printf("  0x%08x\n", state[k]);		\
       OUT_BATCH(state[k]);				\
+   }							\
    ADVANCE_BATCH();					\
-} while (0);
+} while (0)
 
 
 /* Push the state into the sarea and/or texture memory.
@@ -432,7 +434,8 @@ static void i830_emit_state( struct intel_context *intel )
 
       if (dirty & I830_UPLOAD_TEXBLEND(i)) {
 	 if (INTEL_DEBUG & DEBUG_STATE) 
-	    fprintf(stderr, "I830_UPLOAD_TEXBLEND(%d):\n", i); 
+	    fprintf(stderr, "I830_UPLOAD_TEXBLEND(%d): %d words\n", i,
+		    state->TexBlendWordsUsed[i]); 
 	 emit( i830, state->TexBlend[i], 
 	       state->TexBlendWordsUsed[i] * 4 );
       }