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freedreno/ir3: put the conversion back for half const to the right place.

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The previous commit leads to match immed values unexpectedly.

This makes constlen for each shader including bvert wrong.
Also fixes atan2 for mediump deqp tests.

Fixes: cbd1f47433 ("freedreno/ir3: convert back to 32-bit values for half constant registers.")

v2: Move conversion up above fabs/fneg modifier handling as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737>
(cherry picked from commit 260bd32b58)
This commit is contained in:
Hyunjun Ko 2019-11-07 05:28:41 +00:00 • committed by Dylan Baker
parent a25c7674aa
commit f3f4751851
2 changed files with 7 additions and 7 deletions
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2
.pick_status.json
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@ -112,7 +112,7 @@
"description": "freedreno/ir3: put the conversion back for half const to the right place.",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "cbd1f47433b7d735e3be5c8126f7f2b9343a1cdf"
},

12
src/freedreno/ir3/ir3_cp.c
View file

@ -305,6 +305,12 @@ lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags
reg = ir3_reg_clone(ctx->shader, reg);
/* Half constant registers seems to handle only 32-bit values
* within floating-point opcodes. So convert back to 32-bit values.
*/
if (f_opcode && (new_flags & IR3_REG_HALF))
reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
/* in some cases, there are restrictions on (abs)/(neg) plus const..
* so just evaluate those and clear the flags:
*/
@ -350,12 +356,6 @@ lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags
swiz = i % 4;
idx = i / 4;
/* Half constant registers seems to handle only 32-bit values
* within floating-point opcodes. So convert back to 32-bit values. */
if (f_opcode && (new_flags & IR3_REG_HALF)) {
reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
}
const_state->immediates[idx].val[swiz] = reg->uim_val;
const_state->immediates_count = idx + 1;
const_state->immediate_idx++;