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https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-31 16:20:13 +01:00
freedreno/ir3: handle const/immed/abs/neg in cp
Be smarter about propagating copies from const or immed, or with abs/neg modifiers. Also, realize that absneg.s and absneg.f are really "fancy" mov instructions. This opens up the possibility to remove more copies. It helps the TGSI frontend a bit, but will be really needed for the NIR f/e which builds everything up in SSA form (ie. will *always* insert a mov from const or immediate). Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
104713d9f2
commit
f370e95421
3 changed files with 316 additions and 33 deletions
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@ -525,6 +525,12 @@ static inline struct ir3_instruction *ssa(struct ir3_register *reg)
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return NULL;
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}
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static inline bool conflicts(struct ir3_instruction *a,
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struct ir3_instruction *b)
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{
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return (a && b) && (a != b);
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}
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static inline bool reg_gpr(struct ir3_register *r)
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{
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if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_ADDR))
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@ -32,29 +32,47 @@
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/*
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* Copy Propagate:
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*
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* We could eventually drop this, if the front-end did not insert any
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* mov's.. For now keeping it as a separate pass since that is less
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* painful than updating the existing frontend. It is expected that
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* with an eventual new NIR based frontend that we won't need this.
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*/
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static void block_cp(struct ir3_block *block);
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static struct ir3_instruction * instr_cp(struct ir3_instruction *instr);
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static bool is_eligible_mov(struct ir3_instruction *instr)
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/* Is it a non-transformative (ie. not type changing) mov? This can
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* also include absneg.s/absneg.f, which for the most part can be
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* treated as a mov (single src argument).
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*/
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static bool is_same_type_mov(struct ir3_instruction *instr)
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{
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struct ir3_register *dst = instr->regs[0];
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/* mov's that write to a0.x or p0.x are special: */
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if (dst->num == regid(REG_P0, 0))
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return false;
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if (dst->num == regid(REG_A0, 0))
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return false;
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if ((instr->category == 1) &&
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(instr->cat1.src_type == instr->cat1.dst_type)) {
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(instr->cat1.src_type == instr->cat1.dst_type))
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return true;
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if ((instr->category == 2) && ((instr->opc == OPC_ABSNEG_F) ||
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(instr->opc == OPC_ABSNEG_S)))
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return true;
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return false;
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}
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/* is it a type preserving mov, with ok flags? */
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static bool is_eligible_mov(struct ir3_instruction *instr, bool allow_flags)
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{
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if (is_same_type_mov(instr)) {
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struct ir3_register *dst = instr->regs[0];
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struct ir3_register *src = instr->regs[1];
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struct ir3_instruction *src_instr = ssa(src);
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if (dst->flags & (IR3_REG_ADDR | IR3_REG_RELATIV))
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return false;
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/* TODO: propagate abs/neg modifiers if possible */
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if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
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IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_RELATIV))
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if (src->flags & IR3_REG_RELATIV)
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return false;
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if (!allow_flags)
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if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
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IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
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return false;
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if (!src_instr)
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return false;
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/* TODO: remove this hack: */
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@ -65,10 +83,270 @@ static bool is_eligible_mov(struct ir3_instruction *instr)
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return false;
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}
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static struct ir3_instruction *
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instr_cp(struct ir3_instruction *instr)
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static unsigned cp_flags(unsigned flags)
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{
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/* only considering these flags (at least for now): */
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flags &= (IR3_REG_CONST | IR3_REG_IMMED |
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IR3_REG_FNEG | IR3_REG_FABS |
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IR3_REG_SNEG | IR3_REG_SABS |
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IR3_REG_BNOT);
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return flags;
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}
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static bool valid_flags(struct ir3_instruction *instr, unsigned n,
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unsigned flags)
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{
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unsigned valid_flags;
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flags = cp_flags(flags);
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/* clear flags that are 'ok' */
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switch (instr->category) {
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case 1:
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case 5:
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/* no flags allowed */
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if (flags)
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return false;
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break;
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case 6:
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valid_flags = IR3_REG_IMMED;
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if (flags & ~valid_flags)
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return false;
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break;
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case 2:
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valid_flags = ir3_cat2_absneg(instr->opc) | IR3_REG_CONST;
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if (ir3_cat2_immed(instr->opc))
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valid_flags |= IR3_REG_IMMED;
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if (flags & ~valid_flags)
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return false;
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if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
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unsigned m = (n ^ 1) + 1;
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/* cannot deal w/ const in both srcs:
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* (note that some cat2 actually only have a single src)
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*/
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if (m < instr->regs_count) {
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struct ir3_register *reg = instr->regs[m];
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if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
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return false;
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if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
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return false;
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}
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/* cannot be const + ABS|NEG: */
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if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
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IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
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return false;
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}
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break;
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case 3:
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valid_flags = ir3_cat3_absneg(instr->opc) | IR3_REG_CONST;
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if (flags & ~valid_flags)
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return false;
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if (flags & IR3_REG_CONST) {
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/* cannot deal w/ const in 2nd src: */
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/* TODO in some common cases, like mad, we can swap
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* first two args.. possibly we should allow that here
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* and fixup in legalize?
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*/
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if (n == 1)
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return false;
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/* cannot be const + ABS|NEG: */
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if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
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IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
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return false;
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}
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break;
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case 4:
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/* seems like blob compiler avoids const as src.. */
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/* TODO double check if this is still the case on a4xx */
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if (flags & IR3_REG_CONST)
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return false;
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if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
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return false;
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break;
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}
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return true;
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}
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/* propagate register flags from src to dst.. negates need special
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* handling to cancel each other out.
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*/
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static void combine_flags(unsigned *dstflags, unsigned srcflags)
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{
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/* if what we are combining into already has (abs) flags,
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* we can drop (neg) from src:
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*/
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if (*dstflags & IR3_REG_FABS)
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srcflags &= ~IR3_REG_FNEG;
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if (*dstflags & IR3_REG_SABS)
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srcflags &= ~IR3_REG_SNEG;
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if (srcflags & IR3_REG_FABS)
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*dstflags |= IR3_REG_FABS;
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if (srcflags & IR3_REG_SABS)
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*dstflags |= IR3_REG_SABS;
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if (srcflags & IR3_REG_FNEG)
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*dstflags ^= IR3_REG_FNEG;
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if (srcflags & IR3_REG_SNEG)
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*dstflags ^= IR3_REG_SNEG;
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if (srcflags & IR3_REG_BNOT)
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*dstflags ^= IR3_REG_BNOT;
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}
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static struct ir3_instruction * instr_cp(struct ir3_instruction *instr, unsigned *flags);
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/**
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* Handle cp for a given src register. This additionally handles
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* the cases of collapsing immedate/const (which replace the src
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* register with a non-ssa src) or collapsing mov's from relative
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* src (which needs to also fixup the address src reference by the
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* instruction).
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*/
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static void
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reg_cp(struct ir3_instruction *instr, struct ir3_register *reg, unsigned n)
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{
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unsigned src_flags = 0, new_flags;
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struct ir3_instruction *src_instr;
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if (is_meta(instr)) {
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/* meta instructions cannot fold up register
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* flags.. they are usually src for texture
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* fetch, etc, where we cannot specify abs/neg
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*/
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reg->instr = instr_cp(reg->instr, NULL);
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return;
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}
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src_instr = instr_cp(reg->instr, &src_flags);
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new_flags = reg->flags;
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combine_flags(&new_flags, src_flags);
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reg->flags = new_flags;
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reg->instr = src_instr;
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if (!valid_flags(instr, n, reg->flags)) {
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/* insert an absneg.f */
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if (reg->flags & (IR3_REG_SNEG | IR3_REG_SABS)) {
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debug_assert(!(reg->flags & (IR3_REG_FNEG | IR3_REG_FABS)));
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reg->instr = ir3_ABSNEG_S(instr->block,
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reg->instr, cp_flags(src_flags));
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} else {
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debug_assert(!(reg->flags & (IR3_REG_SNEG | IR3_REG_SABS)));
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reg->instr = ir3_ABSNEG_F(instr->block,
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reg->instr, cp_flags(src_flags));
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}
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reg->flags &= ~cp_flags(src_flags);
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/* send it through instr_cp() again since
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* the absneg src might be a mov from const
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* that could be cleaned up:
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*/
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reg->instr = instr_cp(reg->instr, NULL);
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return;
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}
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if (is_same_type_mov(reg->instr)) {
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struct ir3_register *src_reg = reg->instr->regs[1];
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unsigned new_flags = src_reg->flags;
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combine_flags(&new_flags, reg->flags);
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if (!valid_flags(instr, n, new_flags))
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return;
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/* Here we handle the special case of mov from
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* CONST and/or RELATIV. These need to be handled
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* specially, because in the case of move from CONST
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* there is no src ir3_instruction so we need to
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* replace the ir3_register. And in the case of
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* RELATIV we need to handle the address register
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* dependency.
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*/
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if (src_reg->flags & IR3_REG_CONST) {
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/* an instruction cannot reference two different
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* address registers:
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*/
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if ((src_reg->flags & IR3_REG_RELATIV) &&
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conflicts(instr->address, reg->instr->address))
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return;
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src_reg->flags = new_flags;
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instr->regs[n+1] = src_reg;
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if (src_reg->flags & IR3_REG_RELATIV)
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instr->address = reg->instr->address;
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return;
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}
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if ((src_reg->flags & IR3_REG_RELATIV) &&
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!conflicts(instr->address, reg->instr->address)) {
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src_reg->flags = new_flags;
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instr->regs[n+1] = src_reg;
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instr->address = reg->instr->address;
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return;
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}
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/* NOTE: seems we can only do immed integers, so don't
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* need to care about float. But we do need to handle
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* abs/neg *before* checking that the immediate requires
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* few enough bits to encode:
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*
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* TODO: do we need to do something to avoid accidentally
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* catching a float immed?
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*/
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if (src_reg->flags & IR3_REG_IMMED) {
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int32_t iim_val = src_reg->iim_val;
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debug_assert((instr->category == 6) ||
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((instr->category == 2) &&
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ir3_cat2_immed(instr->opc)));
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if (new_flags & IR3_REG_SABS)
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iim_val = abs(iim_val);
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if (new_flags & IR3_REG_SNEG)
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iim_val = -iim_val;
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if (new_flags & IR3_REG_BNOT)
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iim_val = ~iim_val;
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if (!(iim_val & ~0x3ff)) {
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new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
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src_reg->flags = new_flags;
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src_reg->iim_val = iim_val;
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instr->regs[n+1] = src_reg;
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}
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return;
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}
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}
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}
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/**
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* Given an SSA src (instruction), return the one with extraneous
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* mov's removed, ie, for (to copy NIR syntax):
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*
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* vec1 ssa1 = fadd <something>, <somethingelse>
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* vec1 ssa2 = fabs ssa1
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* vec1 ssa3 = fneg ssa1
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*
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* then calling instr_cp(ssa3, &flags) would return ssa1 with
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* (IR3_REG_ABS | IR3_REG_NEGATE) in flags. If flags is NULL,
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* then disallow eliminating copies which would require flag
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* propagation (for example, we cannot propagate abs/neg into
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* an output).
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*/
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static struct ir3_instruction *
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instr_cp(struct ir3_instruction *instr, unsigned *flags)
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{
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struct ir3_register *reg;
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/* stay within the block.. don't try to operate across
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* basic block boundaries or we'll have problems when
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* dealing with multiple basic blocks:
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@ -76,9 +354,12 @@ instr_cp(struct ir3_instruction *instr)
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if (is_meta(instr) && (instr->opc == OPC_META_INPUT))
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return instr;
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if (is_eligible_mov(instr)) {
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struct ir3_instruction *src_instr = ssa(instr->regs[1]);
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return instr_cp(src_instr);
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if (is_eligible_mov(instr, !!flags)) {
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struct ir3_register *reg = instr->regs[1];
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struct ir3_instruction *src_instr = ssa(reg);
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if (flags)
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combine_flags(flags, reg->flags);
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return instr_cp(src_instr, flags);
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}
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/* Check termination condition before walking children (rather
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@ -89,18 +370,20 @@ instr_cp(struct ir3_instruction *instr)
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* up as a src, we only need to recursively walk the children
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* once.)
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*/
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if (!ir3_instr_check_mark(instr)) {
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struct ir3_register *reg;
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if (ir3_instr_check_mark(instr))
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return instr;
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/* walk down the graph from each src: */
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foreach_src(reg, instr)
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if (reg->flags & IR3_REG_SSA)
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reg->instr = instr_cp(reg->instr);
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/* walk down the graph from each src: */
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foreach_src_n(reg, n, instr) {
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if (!(reg->flags & IR3_REG_SSA))
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continue;
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if (instr->address)
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instr->address = instr_cp(instr->address);
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reg_cp(instr, reg, n);
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}
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if (instr->address)
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instr->address = instr_cp(instr->address, NULL);
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return instr;
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}
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@ -111,7 +394,7 @@ static void block_cp(struct ir3_block *block)
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for (i = 0; i < block->noutputs; i++) {
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if (block->outputs[i]) {
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struct ir3_instruction *out =
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instr_cp(block->outputs[i]);
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instr_cp(block->outputs[i], NULL);
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block->outputs[i] = out;
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}
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@ -118,12 +118,6 @@ static void instr_insert_mov(void *arr, int idx, struct ir3_instruction *instr)
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static struct group_ops instr_ops = { instr_get, instr_insert_mov };
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static bool conflicts(struct ir3_instruction *a, struct ir3_instruction *b)
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{
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return (a && b) && (a != b);
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}
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static void group_n(struct group_ops *ops, void *arr, unsigned n)
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{
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unsigned i, j;
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