From f3593df877f84fd2ed2a565b66ecab322cd8c3f1 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Sat, 6 Jul 2024 09:18:44 -0700 Subject: [PATCH] brw/nir: Treat load_reloc_const_intel as convergent shader-db: Lunar Lake, Meteor Lake, DG2, and Tiger Lake had similar results. (Lunar Lake shown) Lunar Lake total instructions in shared programs: 18096549 -> 18096537 (<.01%) instructions in affected programs: 26128 -> 26116 (-0.05%) helped: 7 / HURT: 2 total cycles in shared programs: 922073090 -> 922093922 (<.01%) cycles in affected programs: 10574198 -> 10595030 (0.20%) helped: 19 / HURT: 76 Ice Lake and Skylake had similar results. (Ice Lake shown) total instructions in shared programs: 20503943 -> 20504053 (<.01%) instructions in affected programs: 23378 -> 23488 (0.47%) helped: 6 / HURT: 5 total cycles in shared programs: 875477036 -> 875480112 (<.01%) cycles in affected programs: 13840528 -> 13843604 (0.02%) helped: 22 / HURT: 55 total spills in shared programs: 4546 -> 4552 (0.13%) spills in affected programs: 8 -> 14 (75.00%) helped: 0 / HURT: 1 total fills in shared programs: 5280 -> 5298 (0.34%) fills in affected programs: 24 -> 42 (75.00%) helped: 0 / HURT: 1 One compute shader in Tomb Raider was hurt for spills and fills. fossil-db: Lunar Lake Totals: Instrs: 141808815 -> 141808714 (-0.00%); split: -0.00%, +0.00% Cycle count: 22185066952 -> 22177889310 (-0.03%); split: -0.05%, +0.02% Spill count: 69859 -> 69892 (+0.05%); split: -0.03%, +0.07% Fill count: 128344 -> 128313 (-0.02%); split: -0.04%, +0.01% Scratch Memory Size: 5833728 -> 5829632 (-0.07%) Totals from 13384 (2.43% of 551446) affected shaders: Instrs: 13852162 -> 13852061 (-0.00%); split: -0.00%, +0.00% Cycle count: 7691993336 -> 7684815694 (-0.09%); split: -0.15%, +0.06% Spill count: 53266 -> 53299 (+0.06%); split: -0.03%, +0.10% Fill count: 96492 -> 96461 (-0.03%); split: -0.05%, +0.02% Scratch Memory Size: 3827712 -> 3823616 (-0.11%) Meteor Lake and DG2 had similar results. (Meteor Lake shown) Totals: Instrs: 152744735 -> 152744298 (-0.00%); split: -0.00%, +0.00% Cycle count: 17400199290 -> 17410258529 (+0.06%); split: -0.01%, +0.07% Max live registers: 31887208 -> 31887206 (-0.00%) Totals from 12435 (1.96% of 633315) affected shaders: Instrs: 13445310 -> 13444873 (-0.00%); split: -0.00%, +0.00% Cycle count: 6941685096 -> 6951744335 (+0.14%); split: -0.03%, +0.18% Max live registers: 1071302 -> 1071300 (-0.00%) Tiger Lake and Ice Lake had similar results. (Tiger Lake shown) Totals: Instrs: 150644063 -> 150643944 (-0.00%); split: -0.00%, +0.00% Cycle count: 15618718733 -> 15622092285 (+0.02%); split: -0.01%, +0.03% Spill count: 58816 -> 58790 (-0.04%) Fill count: 101054 -> 101065 (+0.01%) Max live registers: 31792771 -> 31792766 (-0.00%); split: -0.00%, +0.00% Totals from 13383 (2.12% of 632544) affected shaders: Instrs: 12016285 -> 12016166 (-0.00%); split: -0.00%, +0.00% Cycle count: 5239956851 -> 5243330403 (+0.06%); split: -0.02%, +0.08% Spill count: 28977 -> 28951 (-0.09%) Fill count: 47568 -> 47579 (+0.02%) Max live registers: 1001554 -> 1001549 (-0.00%); split: -0.00%, +0.00% Skylake Totals: Instrs: 140943195 -> 140943154 (-0.00%); split: -0.00%, +0.00% Cycle count: 14818940190 -> 14816706154 (-0.02%); split: -0.02%, +0.00% Max live registers: 31663173 -> 31663168 (-0.00%); split: -0.00%, +0.00% Totals from 12625 (2.01% of 629351) affected shaders: Instrs: 11598223 -> 11598182 (-0.00%); split: -0.00%, +0.00% Cycle count: 4519027823 -> 4516793787 (-0.05%); split: -0.05%, +0.00% Max live registers: 970275 -> 970270 (-0.00%); split: -0.00%, +0.00% Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 840c9fde41d..d76a8f84b2b 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1978,6 +1978,7 @@ get_nir_def(nir_to_brw_state &ntb, const nir_def &def, bool all_sources_uniform) switch (instr->intrinsic) { case nir_intrinsic_load_inline_data_intel: + case nir_intrinsic_load_reloc_const_intel: case nir_intrinsic_load_workgroup_id: is_scalar = true; break; @@ -5030,13 +5031,7 @@ try_rebuild_source(nir_to_brw_state &ntb, const brw::fs_builder &bld, } case nir_intrinsic_load_reloc_const_intel: { - uint32_t id = nir_intrinsic_param_idx(intrin); - uint32_t base = nir_intrinsic_base(intrin); - brw_reg dst = ubld.vgrf(BRW_TYPE_D); - ntb.resource_insts[def->index] = - ubld.emit(SHADER_OPCODE_MOV_RELOC_IMM, dst, - brw_imm_ud(id), brw_imm_ud(base)); - break; + unreachable("load_reloc_const_intel should already be is_scalar"); } case nir_intrinsic_load_ubo_uniform_block_intel: @@ -6389,15 +6384,10 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, uint32_t id = nir_intrinsic_param_idx(instr); uint32_t base = nir_intrinsic_base(instr); - /* Emit the reloc in the smallest SIMD size to limit register usage. */ - const fs_builder ubld = bld.exec_all().group(1, 0); - brw_reg small_dest = ubld.vgrf(dest.type); - ubld.UNDEF(small_dest); - ubld.exec_all().group(1, 0).emit(SHADER_OPCODE_MOV_RELOC_IMM, small_dest, - brw_imm_ud(id), brw_imm_ud(base)); + assert(dest.is_scalar); - /* Copy propagation will get rid of this MOV. */ - bld.MOV(dest, component(small_dest, 0)); + xbld.emit(SHADER_OPCODE_MOV_RELOC_IMM, retype(dest, BRW_TYPE_D), + brw_imm_ud(id), brw_imm_ud(base)); break; }