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r600/sfn: copy propagate register load chains
NIR sometimes produces load chains like r0 mov value r1 mov r0 r2 mov r1 Add copy propagation for these cases Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
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2 changed files with 40 additions and 11 deletions
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@ -350,13 +350,38 @@ void CopyPropFwdVisitor::visit(AluInstr *instr)
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auto src = instr->psrc(0);
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auto src = instr->psrc(0);
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auto dest = instr->dest();
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auto dest = instr->dest();
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for (auto& i : instr->dest()->uses()) {
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for (auto& i : dest->uses()) {
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/* SSA can always be propagated, registers only in the same block
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/* SSA can always be propagated, registers only in the same block
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* and only if they are not assigned to more than once */
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* and only if they are assigned in the same block */
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if (dest->is_ssa() ||
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bool can_propagate = dest->is_ssa();
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(instr->block_id() == i->block_id() &&
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instr->index() < i->index() &&
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if (!can_propagate) {
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dest->uses().size() == 1)) {
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/* Register can propagate if the assigment was in the same
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* block, and we don't have a second assignment coming later
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* (e.g. helper invocation evaluation does
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*
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* 1: MOV R0.x, -1
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* 2: FETCH R0.0 VPM
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* 3: MOV SN.x, R0.x
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*
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* Here we can't prpagate the move in 1 to SN.x in 3 */
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if ((instr->block_id() == i->block_id() &&
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instr->index() < i->index())) {
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can_propagate = true;
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if (dest->parents().size() > 1) {
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for (auto p : dest->parents()) {
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if (p->block_id() == i->block_id() &&
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p->index() > instr->index()) {
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can_propagate = false;
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break;
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}
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}
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}
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}
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}
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if (can_propagate) {
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sfn_log << SfnLog::opt << " Try replace in "
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sfn_log << SfnLog::opt << " Try replace in "
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<< i->block_id() << ":" << i->index()
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<< i->block_id() << ":" << i->index()
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<< *i<< "\n";
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<< *i<< "\n";
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@ -584,8 +609,12 @@ void SimplifySourceVecVisitor::visit(TexInstr *instr)
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++nvals;
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++nvals;
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if (nvals == 1) {
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if (nvals == 1) {
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for (int i = 0; i < 4; ++i)
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for (int i = 0; i < 4; ++i)
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if (src[i]->chan() < 4)
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if (src[i]->chan() < 4) {
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src[i]->set_pin(pin_free);
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if (src[i]->pin() == pin_group)
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src[i]->set_pin(pin_free);
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else if (src[i]->pin() == pin_chgr)
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src[i]->set_pin(pin_chan);
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}
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}
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}
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}
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}
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for (auto& prep : instr->prepare_instr()) {
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for (auto& prep : instr->prepare_instr()) {
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@ -1121,18 +1121,18 @@ IF (( ALU PREDE_INT __.x@free : KC0[0].x I[1] {LEP} PUSH_BEFORE ))
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ALU MOV R3.x : R5.x {WL}
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ALU MOV R3.x : R5.x {WL}
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LOOP_END
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LOOP_END
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ALU MOV R8.x : I[1.0] {WL}
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ALU MOV R8.x : I[1.0] {WL}
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ALU MOV R7.x : R8.x {WL}
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ALU MOV R7.x : I[1.0] {WL}
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ALU MOV R6.x : I[-1] {WL}
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ALU MOV R6.x : I[-1] {WL}
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ELSE
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ELSE
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ALU MOV R8.x : I[1.0] {WL}
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ALU MOV R8.x : I[1.0] {WL}
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ALU MOV R7.x : I[0] {WL}
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ALU MOV R7.x : I[0] {WL}
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ALU MOV R4.x : R8.x {WL}
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ALU MOV R4.x : I[1.0] {WL}
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ALU MOV R6.x : I[0] {WL}
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ALU MOV R6.x : I[0] {WL}
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ENDIF
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ENDIF
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ELSE
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ELSE
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ALU MOV R8.x : I[1.0] {WL}
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ALU MOV R8.x : I[1.0] {WL}
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ALU MOV R7.x : I[0] {WL}
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ALU MOV R7.x : I[0] {WL}
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ALU MOV R4.x : R8.x {WL}
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ALU MOV R4.x : I[1.0] {WL}
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ALU MOV R6.x : I[-1] {WL}
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ALU MOV R6.x : I[-1] {WL}
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ENDIF
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ENDIF
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ALU CNDE_INT S27.x@free : R6.x I[1.0] R4.x {WL}
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ALU CNDE_INT S27.x@free : R6.x I[1.0] R4.x {WL}
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