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i965: Fix INTEL_DEBUG=shader_time for Haswell.

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Haswell's "Data Cache" data port is a single unit, but split into two
SFIDs to allow for more message types without adding more bits in the
message descriptor.

Untyped Atomic Operations are now message 0010 in the second data cache
data port, rather than 6 in the first.

v2: Use the #defines from the previous commit. (by anholt)

NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
(cherry picked from commit f27a220cad)
This commit is contained in:
Kenneth Graunke 2013-02-06 23:26:34 -08:00 • committed by Ian Romanick
parent 74e8838179
commit f32e776efb
2 changed files with 12 additions and 4 deletions
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1
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -857,6 +857,7 @@ enum brw_message_target {
GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
GEN7_SFID_DATAPORT_DATA_CACHE = 10,
HSW_SFID_DATAPORT_DATA_CACHE_1 = 12,
};
#define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10

15
src/mesa/drivers/dri/i965/brw_eu_emit.c
View file

@ -2539,15 +2539,22 @@ void brw_shader_time_add(struct brw_compile *p,
brw_set_src0(p, send, brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
base_mrf, 0));
uint32_t sfid, msg_type;
if (intel->is_haswell) {
sfid = HSW_SFID_DATAPORT_DATA_CACHE_1;
msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
} else {
sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
}
bool header_present = false;
bool eot = false;
uint32_t mlen = 2; /* offset, value */
uint32_t rlen = 0;
brw_set_message_descriptor(p, send,
GEN7_SFID_DATAPORT_DATA_CACHE,
mlen, rlen, header_present, eot);
brw_set_message_descriptor(p, send, sfid, mlen, rlen, header_present, eot);
send->bits3.ud |= 6 << 14; /* untyped atomic op */
send->bits3.ud |= msg_type << 14;
send->bits3.ud |= 0 << 13; /* no return data */
send->bits3.ud |= 1 << 12; /* SIMD8 mode */
send->bits3.ud |= BRW_AOP_ADD << 8;