diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index da35a2e66a3..e595e83ef57 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -1491,27 +1491,6 @@ struct drm_amdgpu_info_hw_ip {
 	__u32  ip_discovery_version;
 };
 
-/* GFX metadata BO sizes and alignment info (in bytes) */
-struct drm_amdgpu_info_uq_fw_areas_gfx {
-	/* shadow area size */
-	__u32 shadow_size;
-	/* shadow area base virtual mem alignment */
-	__u32 shadow_alignment;
-	/* context save area size */
-	__u32 csa_size;
-	/* context save area base virtual mem alignment */
-	__u32 csa_alignment;
-};
-
-/* IP specific metadata related information used in the
- * subquery AMDGPU_INFO_UQ_FW_AREAS
- */
-struct drm_amdgpu_info_uq_fw_areas {
-	union {
-		struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
-	};
-};
-
 struct drm_amdgpu_info_num_handles {
 	/** Max handles as supported by firmware for UVD */
 	__u32  uvd_max_handles;
@@ -1575,6 +1554,39 @@ struct drm_amdgpu_info_gpuvm_fault {
 	__u32 vmhub;
 };
 
+struct drm_amdgpu_info_uq_metadata_gfx {
+	/* shadow area size for gfx11 */
+	__u32 shadow_size;
+	/* shadow area base virtual alignment for gfx11 */
+	__u32 shadow_alignment;
+	/* context save area size for gfx11 */
+	__u32 csa_size;
+	/* context save area base virtual alignment for gfx11 */
+	__u32 csa_alignment;
+};
+
+struct drm_amdgpu_info_uq_metadata_compute {
+	/* EOP size for gfx11 */
+	__u32 eop_size;
+	/* EOP base virtual alignment for gfx11 */
+	__u32 eop_alignment;
+};
+
+struct drm_amdgpu_info_uq_metadata_sdma {
+	/* context save area size for sdma6 */
+	__u32 csa_size;
+	/* context save area base virtual alignment for sdma6 */
+	__u32 csa_alignment;
+};
+
+struct drm_amdgpu_info_uq_metadata {
+	union {
+		struct drm_amdgpu_info_uq_metadata_gfx gfx;
+		struct drm_amdgpu_info_uq_metadata_compute compute;
+		struct drm_amdgpu_info_uq_metadata_sdma sdma;
+	};
+};
+
 /*
  * Supported GPU families
  */
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 0aedd1e8a45..c36e480b5a0 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -1465,7 +1465,7 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
    }
 
    if (info->gfx_level >= GFX11 && (info->userq_ip_mask & (1 << AMD_IP_GFX))) {
-      struct drm_amdgpu_info_uq_fw_areas fw_info;
+      struct drm_amdgpu_info_uq_metadata fw_info;
 
       r = ac_drm_query_uq_fw_area_info(dev, AMDGPU_HW_IP_GFX, 0, &fw_info);
       if (r) {
diff --git a/src/amd/common/ac_linux_drm.c b/src/amd/common/ac_linux_drm.c
index 58ec936ce71..777c1346530 100644
--- a/src/amd/common/ac_linux_drm.c
+++ b/src/amd/common/ac_linux_drm.c
@@ -652,13 +652,20 @@ int ac_drm_query_firmware_version(ac_drm_device *dev, unsigned fw_type, unsigned
 }
 
 int ac_drm_query_uq_fw_area_info(ac_drm_device *dev, unsigned type, unsigned ip_instance,
-                                 struct drm_amdgpu_info_uq_fw_areas *info)
+                                 struct drm_amdgpu_info_uq_metadata *info)
 {
    struct drm_amdgpu_info request;
 
    memset(&request, 0, sizeof(request));
    request.return_pointer = (uintptr_t)info;
-   request.return_size = sizeof(*info);
+   if (type == AMDGPU_HW_IP_GFX)
+      request.return_size = sizeof(struct drm_amdgpu_info_uq_metadata_gfx);
+   else if (type == AMDGPU_HW_IP_COMPUTE)
+      request.return_size = sizeof(struct drm_amdgpu_info_uq_metadata_compute);
+   else if (type == AMDGPU_HW_IP_DMA)
+      request.return_size = sizeof(struct drm_amdgpu_info_uq_metadata_sdma);
+   else
+      UNREACHABLE("invalid type");
    request.query = AMDGPU_INFO_UQ_FW_AREAS;
    request.query_hw_ip.type = type;
    request.query_hw_ip.ip_instance = ip_instance;
diff --git a/src/amd/common/ac_linux_drm.h b/src/amd/common/ac_linux_drm.h
index fa61ef9ce24..9ea563cc8c6 100644
--- a/src/amd/common/ac_linux_drm.h
+++ b/src/amd/common/ac_linux_drm.h
@@ -196,16 +196,36 @@ struct drm_amdgpu_info_hw_ip {
    uint32_t ip_discovery_version;
 };
 
-struct drm_amdgpu_info_uq_fw_areas_gfx {
+struct drm_amdgpu_info_uq_metadata_gfx {
+   /* shadow area size for gfx11 */
    uint32_t shadow_size;
+   /* shadow area base virtual alignment for gfx11 */
    uint32_t shadow_alignment;
+   /* context save area size for gfx11 */
    uint32_t csa_size;
+   /* context save area base virtual alignment for gfx11 */
    uint32_t csa_alignment;
 };
 
-struct drm_amdgpu_info_uq_fw_areas {
+struct drm_amdgpu_info_uq_metadata_compute {
+   /* EOP size for gfx11 */
+   uint32_t eop_size;
+   /* EOP base virtual alignment for gfx11 */
+   uint32_t eop_alignment;
+};
+
+struct drm_amdgpu_info_uq_metadata_sdma {
+   /* context save area size for sdma6 */
+   uint32_t csa_size;
+   /* context save area base virtual alignment for sdma6 */
+   uint32_t csa_alignment;
+};
+
+struct drm_amdgpu_info_uq_metadata {
    union {
-      struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
+      struct drm_amdgpu_info_uq_metadata_gfx gfx;
+      struct drm_amdgpu_info_uq_metadata_compute compute;
+      struct drm_amdgpu_info_uq_metadata_sdma sdma;
    };
 };
 
@@ -405,7 +425,7 @@ PROC int ac_drm_query_hw_ip_info(ac_drm_device *dev, unsigned type, unsigned ip_
 PROC int ac_drm_query_firmware_version(ac_drm_device *dev, unsigned fw_type, unsigned ip_instance,
                                        unsigned index, uint32_t *version, uint32_t *feature) TAIL;
 PROC int ac_drm_query_uq_fw_area_info(ac_drm_device *dev, unsigned type, unsigned ip_instance,
-                                      struct drm_amdgpu_info_uq_fw_areas *info) TAIL;
+                                      struct drm_amdgpu_info_uq_metadata *info) TAIL;
 PROC int ac_drm_query_gpu_info(ac_drm_device *dev, struct amdgpu_gpu_info *info) TAIL;
 PROC int ac_drm_query_heap_info(ac_drm_device *dev, uint32_t heap, uint32_t flags,
                                 struct amdgpu_heap_info *info) TAIL;