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tu: Set TU_ACCESS_CCHE_READ for transfer ops with read access

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Transfer ops also use CCHE since they use the same path as
texture access.

This addresses the flakiness seen in
KHR-GL46.shader_storage_buffer_object.advanced-usage-sync-cs
CCHE wasn't being invalidated between the compute op and transfer
op which would sometimes lead to old/invalid data to be copied
in the transfer op.

Fixes: fb1c3f7f5d ("tu: Implement CCHE invalidation")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11458
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30490>
(cherry picked from commit cf9588bae6)
This commit is contained in:
Karmjit Mahil 2024-08-02 17:13:39 +02:00 • committed by Eric Engestrom
parent 05f1c0b9ea
commit f3195e77dc
2 changed files with 2 additions and 2 deletions
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2
.pick_status.json
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@ -5524,7 +5524,7 @@
"description": "tu: Set `TU_ACCESS_CCHE_READ` for transfer ops with read access",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "fb1c3f7f5de6642fcd127724a0cea5643d39d7ee",
"notes": null

2
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -3597,7 +3597,7 @@ vk2tu_access(VkAccessFlags2 flags, VkPipelineStageFlags2 stages, bool image_only
VK_PIPELINE_STAGE_2_BLIT_BIT |
VK_PIPELINE_STAGE_2_RESOLVE_BIT |
VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT)) {
mask |= TU_ACCESS_UCHE_READ;
mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_CCHE_READ;
}
return mask;