i965: Perform basic optimizations on the BROADCAST opcode.

v2: Style fixes.

Reviewed-by: Matt Turner <mattst88@gmail.com>

src/mesa/drivers/dri/i965/brw_fs.cpp

@@ -2546,6 +2546,22 @@ fs_visitor::opt_algebraic()
          }
          break;
       }
+      case SHADER_OPCODE_BROADCAST:
+         if (is_uniform(inst->src[0])) {
+            inst->opcode = BRW_OPCODE_MOV;
+            inst->sources = 1;
+            inst->force_writemask_all = true;
+            progress = true;
+         } else if (inst->src[1].file == IMM) {
+            inst->opcode = BRW_OPCODE_MOV;
+            inst->src[0] = component(inst->src[0],
+                                     inst->src[1].fixed_hw_reg.dw1.ud);
+            inst->sources = 1;
+            inst->force_writemask_all = true;
+            progress = true;
+         }
+         break;
+
       default:
 	 break;
       }

src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp

@@ -608,6 +608,7 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
          break;
 
       case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
+      case SHADER_OPCODE_BROADCAST:
          inst->src[i] = val;
          progress = true;
          break;

src/mesa/drivers/dri/i965/brw_fs_cse.cpp

@@ -89,6 +89,7 @@ is_expression(const fs_inst *const inst)
    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
    case FS_OPCODE_CINTERP:
    case FS_OPCODE_LINTERP:
+   case SHADER_OPCODE_BROADCAST:
       return true;
    case SHADER_OPCODE_RCP:
    case SHADER_OPCODE_RSQ:

src/mesa/drivers/dri/i965/brw_ir_fs.h

@@ -166,6 +166,13 @@ component(fs_reg reg, unsigned idx)
    return reg;
 }
 
+static inline bool
+is_uniform(const fs_reg &reg)
+{
+   return (reg.width == 1 || reg.stride == 0 || reg.is_null()) &&
+          (!reg.reladdr || is_uniform(*reg.reladdr));
+}
+
 /**
  * Get either of the 8-component halves of a 16-component register.
  *

src/mesa/drivers/dri/i965/brw_ir_vec4.h

@@ -95,6 +95,13 @@ negate(src_reg reg)
    return reg;
 }
 
+static inline bool
+is_uniform(const src_reg &reg)
+{
+   return (reg.file == IMM || reg.file == UNIFORM || reg.is_null()) &&
+          (!reg.reladdr || is_uniform(*reg.reladdr));
+}
+
 class dst_reg : public backend_reg
 {
 public:

src/mesa/drivers/dri/i965/brw_vec4.cpp

@@ -682,6 +682,16 @@ vec4_visitor::opt_algebraic()
          }
          break;
       }
+      case SHADER_OPCODE_BROADCAST:
+         if (is_uniform(inst->src[0]) ||
+             inst->src[1].is_zero()) {
+            inst->opcode = BRW_OPCODE_MOV;
+            inst->src[1] = src_reg();
+            inst->force_writemask_all = true;
+            progress = true;
+         }
+         break;
+
       default:
 	 break;
       }

src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

@@ -152,6 +152,7 @@ try_constant_propagate(const struct brw_device_info *devinfo,
 
    switch (inst->opcode) {
    case BRW_OPCODE_MOV:
+   case SHADER_OPCODE_BROADCAST:
       inst->src[arg] = value;
       return true;
 

src/mesa/drivers/dri/i965/brw_vec4_cse.cpp

@@ -72,6 +72,7 @@ is_expression(const vec4_instruction *const inst)
    case BRW_OPCODE_MAD:
    case BRW_OPCODE_LRP:
    case VEC4_OPCODE_UNPACK_UNIFORM:
+   case SHADER_OPCODE_BROADCAST:
       return true;
    case SHADER_OPCODE_RCP:
    case SHADER_OPCODE_RSQ: