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i965/vec4: Don't coalesce regs in Gen6 MATH ops if reswizzle/writemask needed

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Gen6 MATH instructions can not execute in align16 mode, so swizzles or
writemasking are not allowed.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92033
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Antia Puentes 2015-09-22 18:17:45 +02:00
parent cf439951b7
commit f2e75ac88a
2 changed files with 12 additions and 3 deletions
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3
src/mesa/drivers/dri/i965/brw_ir_vec4.h
View file

@ -175,7 +175,8 @@ public:
bool is_send_from_grf();
unsigned regs_read(unsigned arg) const;
bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
bool can_reswizzle(const struct brw_device_info *devinfo, int dst_writemask,
int swizzle, int swizzle_mask);
void reswizzle(int dst_writemask, int swizzle);
bool can_do_source_mods(const struct brw_device_info *devinfo);

12
src/mesa/drivers/dri/i965/brw_vec4.cpp
View file

@ -941,10 +941,18 @@ vec4_visitor::opt_set_dependency_control()
}
bool
vec4_instruction::can_reswizzle(int dst_writemask,
vec4_instruction::can_reswizzle(const struct brw_device_info *devinfo,
int dst_writemask,
int swizzle,
int swizzle_mask)
{
/* Gen6 MATH instructions can not execute in align16 mode, so swizzles
* or writemasking are not allowed.
*/
if (devinfo->gen == 6 && is_math() &&
(swizzle != BRW_SWIZZLE_XYZW || dst_writemask != WRITEMASK_XYZW))
return false;
/* If this instruction sets anything not referenced by swizzle, then we'd
* totally break it when we reswizzle.
*/
@ -1099,7 +1107,7 @@ vec4_visitor::opt_register_coalesce()
break;
/* If we can't handle the swizzle, bail. */
if (!scan_inst->can_reswizzle(inst->dst.writemask,
if (!scan_inst->can_reswizzle(devinfo, inst->dst.writemask,
inst->src[0].swizzle,
chans_needed)) {
break;