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anv: allocator: correct scratch space for haswell
This reproduces this commit :
commit 2213ffdb4b
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Mon Jun 6 21:37:34 2016 -0700
i965: Allocate scratch space for the maximum number of compute threads.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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1 changed files with 21 additions and 1 deletions
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@ -926,13 +926,33 @@ anv_scratch_pool_alloc(struct anv_device *device, struct anv_scratch_pool *pool,
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struct anv_physical_device *physical_device =
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&device->instance->physicalDevice;
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/* WaCSScratchSize:hsw
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*
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* Haswell's scratch space address calculation appears to be sparse
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* rather than tightly packed. The Thread ID has bits indicating which
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* subslice, EU within a subslice, and thread within an EU it is.
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* There's a maximum of two slices and two subslices, so these can be
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* stored with a single bit. Even though there are only 10 EUs per
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* subslice, this is stored in 4 bits, so there's an effective maximum
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* value of 16 EUs. Similarly, although there are only 7 threads per EU,
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* this is stored in a 3 bit number, giving an effective maximum value
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* of 8 threads per EU.
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*
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* This means that we need to use 16 * 8 instead of 10 * 7 for the
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* number of threads per subslice.
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*/
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const unsigned subslices = MAX2(physical_device->subslice_total, 1);
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const unsigned scratch_ids_per_subslice =
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device->info.is_haswell ? 16 * 8 : physical_device->max_cs_threads;
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uint32_t max_threads[] = {
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[MESA_SHADER_VERTEX] = physical_device->max_vs_threads,
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[MESA_SHADER_TESS_CTRL] = physical_device->max_hs_threads,
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[MESA_SHADER_TESS_EVAL] = physical_device->max_ds_threads,
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[MESA_SHADER_GEOMETRY] = physical_device->max_gs_threads,
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[MESA_SHADER_FRAGMENT] = physical_device->max_wm_threads,
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[MESA_SHADER_COMPUTE] = physical_device->max_cs_threads,
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[MESA_SHADER_COMPUTE] = scratch_ids_per_subslice * subslices,
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};
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size = per_thread_scratch * max_threads[stage];
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