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i965: Refactor fs_generator API

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We split out SIMD8 and SIMD16 generation into seperate calls to
new method generate_code(), which returns the start offset for the
generated code.  A new get_assembly() method returns the generated code.

This avoids asserting MESA_SHADER_FRAGMENT and accessing wm_prog_data
in the generator.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Kristian Høgsberg 2014-11-13 16:28:08 -08:00 • committed by Kenneth Graunke
parent 13849f327c
commit f2bb655ac7
4 changed files with 23 additions and 39 deletions
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4
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
View file

@ -45,7 +45,9 @@ const unsigned *
brw_blorp_eu_emitter::get_program(unsigned *program_size)
{
cfg_t cfg(&insts);
return generator.generate_assembly(NULL, &cfg, program_size);
generator.generate_code(&cfg, 16);
return generator.get_assembly(program_size);
}
/**

9
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -3729,11 +3729,12 @@ brw_wm_fs_emit(struct brw_context *brw,
prog_data->no_8 = false;
}
const unsigned *assembly = NULL;
fs_generator g(brw, mem_ctx, key, prog_data, prog, fp,
v.runtime_check_aads_emit, INTEL_DEBUG & DEBUG_WM);
assembly = g.generate_assembly(simd8_cfg, simd16_cfg,
final_assembly_size);
if (simd8_cfg)
g.generate_code(simd8_cfg, 8);
if (simd16_cfg)
prog_data->prog_offset_16 = g.generate_code(simd16_cfg, 16);
if (unlikely(brw->perf_debug) && shader) {
if (shader->compiled_once)
@ -3746,7 +3747,7 @@ brw_wm_fs_emit(struct brw_context *brw,
}
}
return assembly;
return g.get_assembly(final_assembly_size);
}
bool

6
src/mesa/drivers/dri/i965/brw_fs.h
View file

@ -697,12 +697,10 @@ public:
bool debug_flag);
~fs_generator();
const unsigned *generate_assembly(const cfg_t *simd8_cfg,
const cfg_t *simd16_cfg,
unsigned *assembly_size);
int generate_code(const cfg_t *cfg, int dispatch_width);
const unsigned *get_assembly(unsigned int *assembly_size);
private:
void generate_code(const cfg_t *cfg);
void fire_fb_write(fs_inst *inst,
struct brw_reg payload,
struct brw_reg implied_header,

43
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
View file

@ -1512,9 +1512,17 @@ fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
brw_mark_surface_used(prog_data, surf_index.dw1.ud);
}
void
fs_generator::generate_code(const cfg_t *cfg)
int
fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
{
/* align to 64 byte boundary. */
while (p->next_insn_offset % 64)
brw_NOP(p);
this->dispatch_width = dispatch_width;
if (dispatch_width == 16)
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
int start_offset = p->next_insn_offset;
int loop_count = 0;
@ -2024,37 +2032,12 @@ fs_generator::generate_code(const cfg_t *cfg)
dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
ralloc_free(annotation.ann);
}
return start_offset;
}
const unsigned *
fs_generator::generate_assembly(const cfg_t *simd8_cfg,
const cfg_t *simd16_cfg,
unsigned *assembly_size)
fs_generator::get_assembly(unsigned int *assembly_size)
{
assert(simd8_cfg || simd16_cfg);
if (simd8_cfg) {
dispatch_width = 8;
generate_code(simd8_cfg);
}
if (simd16_cfg) {
/* align to 64 byte boundary. */
while (p->next_insn_offset % 64) {
brw_NOP(p);
}
assert(stage == MESA_SHADER_FRAGMENT);
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
/* Save off the start of this SIMD16 program */
prog_data->prog_offset_16 = p->next_insn_offset;
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
dispatch_width = 16;
generate_code(simd16_cfg);
}
return brw_get_program(p, assembly_size);
}