fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-24 00:10:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

tu: Fix VS primid with tess + GS

Browse source 
If tess is enabled, then VS chains to the HS and we have to use the HS
value for the PrimID sysval. This is still true if GS is also enabled,
so we need to use the HS instead of the GS if both are enabled.  In
particular if the HS or DS uses gl_PrimitiveID but the GS doesn't then
we still need to setup the register.

This fixes a bunch of dEQP-VK.tessellation.invariance.primitive_set.*
cases on a650, although it seems they managed to still pass on a630 with
the broken PrimID handling.

Fixes: 8115cde3ba ("tu, freedreno/a6xx, ir3: Rewrite tess PrimID handling")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12768>
This commit is contained in:
Connor Abbott 2021-09-08 14:59:28 +02:00 • committed by Marge Bot
parent c1f724b2b9
commit f254686b13
1 changed files with 2 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/freedreno/vulkan/tu_pipeline.c
View file

@ -680,11 +680,9 @@ tu6_emit_vs_system_values(struct tu_cs *cs,
const uint32_t gs_primitiveid_regid = gs ?
ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
regid(63, 0);
const uint32_t hs_primitiveid_regid = hs ?
const uint32_t vs_primitiveid_regid = hs ?
ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID) :
regid(63, 0);
const uint32_t vs_primitiveid_regid = gs ? gs_primitiveid_regid :
hs_primitiveid_regid;
gs_primitiveid_regid;
const uint32_t ds_primitiveid_regid = ds ?
ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID) :
regid(63, 0);