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https://gitlab.freedesktop.org/mesa/mesa.git
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freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
6d9849d63e
commit
f20013a119
7 changed files with 334 additions and 63 deletions
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@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 33379 bytes, from 2017-11-14 21:00:47)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13612 bytes, from 2017-11-28 14:06:11)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 34499 bytes, from 2017-12-17 17:36:55)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 143420 bytes, from 2017-11-16 20:29:34)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2017-11-28 14:06:11)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 145953 bytes, from 2017-12-17 17:36:55)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
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Copyright (C) 2013-2017 by the following authors:
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@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 33379 bytes, from 2017-11-14 21:00:47)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13612 bytes, from 2017-11-28 14:06:11)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 34499 bytes, from 2017-12-17 17:36:55)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 143420 bytes, from 2017-11-16 20:29:34)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2017-11-28 14:06:11)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 145953 bytes, from 2017-12-17 17:36:55)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
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Copyright (C) 2013-2017 by the following authors:
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@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 33379 bytes, from 2017-11-14 21:00:47)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13612 bytes, from 2017-11-28 14:06:11)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 34499 bytes, from 2017-12-17 17:36:55)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 143420 bytes, from 2017-11-16 20:29:34)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2017-11-28 14:06:11)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 145953 bytes, from 2017-12-17 17:36:55)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
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Copyright (C) 2013-2017 by the following authors:
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@ -263,12 +263,6 @@ enum a4xx_depth_format {
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DEPTH4_32 = 3,
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};
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enum a4xx_tess_spacing {
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EQUAL_SPACING = 0,
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ODD_SPACING = 2,
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EVEN_SPACING = 3,
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};
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enum a4xx_ccu_perfcounter_select {
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CCU_BUSY_CYCLES = 0,
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CCU_RB_DEPTH_RETURN_STALL = 2,
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@ -3558,12 +3552,13 @@ static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
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}
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#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
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#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
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#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
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static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE 0x00008000
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#define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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@ -3585,12 +3580,13 @@ static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
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}
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#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
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#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
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#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
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static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE 0x00008000
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#define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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@ -3612,12 +3608,13 @@ static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
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}
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#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
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#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
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#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
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static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE 0x00008000
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#define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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@ -3639,12 +3636,13 @@ static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
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}
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#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
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#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
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#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
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static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE 0x00008000
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#define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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@ -3666,12 +3664,13 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
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}
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#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
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#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
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#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
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static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE 0x00008000
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#define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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@ -3686,23 +3685,103 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
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return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
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}
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#define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca
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#define REG_A4XX_HLSQ_CS_CONTROL_REG 0x000023ca
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#define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
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#define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT 0
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static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK;
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}
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#define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
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#define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
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static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE 0x00008000
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#define A4XX_HLSQ_CS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK;
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}
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#define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
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#define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT 24
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static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK;
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}
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#define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
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#define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK 0x00000003
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#define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT 0
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static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK;
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}
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#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
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#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT 2
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static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK;
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}
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#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
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#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT 12
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static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK;
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}
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#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
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#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT 22
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static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK;
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}
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#define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
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#define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK 0xffffffff
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#define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT 0
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static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT) & A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK;
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}
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#define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
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#define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
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#define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK 0xffffffff
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#define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT 0
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static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT) & A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK;
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}
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#define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
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#define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
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#define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK 0xffffffff
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#define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT 0
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static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT) & A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK;
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}
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#define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
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#define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
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#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x000000ff
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#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT 0
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static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK;
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}
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#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK 0xff000000
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#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT 24
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static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)
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{
|
||||
return ((val) << A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
|
||||
|
||||
|
|
@ -4104,5 +4183,73 @@ static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
|
|||
|
||||
#define REG_A4XX_TEX_CONST_7 0x00000007
|
||||
|
||||
#define REG_A4XX_SSBO_0_0 0x00000000
|
||||
#define A4XX_SSBO_0_0_BASE__MASK 0xffffffe0
|
||||
#define A4XX_SSBO_0_0_BASE__SHIFT 5
|
||||
static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val)
|
||||
{
|
||||
assert(!(val & 0x1f));
|
||||
return ((val >> 5) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_SSBO_0_1 0x00000001
|
||||
#define A4XX_SSBO_0_1_PITCH__MASK 0x003fffff
|
||||
#define A4XX_SSBO_0_1_PITCH__SHIFT 0
|
||||
static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_0_1_PITCH__SHIFT) & A4XX_SSBO_0_1_PITCH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_SSBO_0_2 0x00000002
|
||||
#define A4XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000
|
||||
#define A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
|
||||
static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
|
||||
{
|
||||
assert(!(val & 0xfff));
|
||||
return ((val >> 12) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_SSBO_0_3 0x00000003
|
||||
#define A4XX_SSBO_0_3_CPP__MASK 0x0000003f
|
||||
#define A4XX_SSBO_0_3_CPP__SHIFT 0
|
||||
static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_0_3_CPP__SHIFT) & A4XX_SSBO_0_3_CPP__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_SSBO_1_0 0x00000000
|
||||
#define A4XX_SSBO_1_0_CPP__MASK 0x0000001f
|
||||
#define A4XX_SSBO_1_0_CPP__SHIFT 0
|
||||
static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_1_0_CPP__SHIFT) & A4XX_SSBO_1_0_CPP__MASK;
|
||||
}
|
||||
#define A4XX_SSBO_1_0_FMT__MASK 0x0000ff00
|
||||
#define A4XX_SSBO_1_0_FMT__SHIFT 8
|
||||
static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_1_0_FMT__SHIFT) & A4XX_SSBO_1_0_FMT__MASK;
|
||||
}
|
||||
#define A4XX_SSBO_1_0_WIDTH__MASK 0xffff0000
|
||||
#define A4XX_SSBO_1_0_WIDTH__SHIFT 16
|
||||
static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_1_0_WIDTH__SHIFT) & A4XX_SSBO_1_0_WIDTH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_SSBO_1_1 0x00000001
|
||||
#define A4XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff
|
||||
#define A4XX_SSBO_1_1_HEIGHT__SHIFT 0
|
||||
static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_1_1_HEIGHT__SHIFT) & A4XX_SSBO_1_1_HEIGHT__MASK;
|
||||
}
|
||||
#define A4XX_SSBO_1_1_DEPTH__MASK 0xffff0000
|
||||
#define A4XX_SSBO_1_1_DEPTH__SHIFT 16
|
||||
static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_1_1_DEPTH__SHIFT) & A4XX_SSBO_1_1_DEPTH__MASK;
|
||||
}
|
||||
|
||||
|
||||
#endif /* A4XX_XML */
|
||||
|
|
|
|||
|
|
@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
|
|||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 33379 bytes, from 2017-11-14 21:00:47)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13612 bytes, from 2017-11-28 14:06:11)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 34499 bytes, from 2017-12-17 17:36:55)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 143420 bytes, from 2017-11-16 20:29:34)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2017-11-28 14:06:11)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 145953 bytes, from 2017-12-17 17:36:55)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
|
|
@ -935,6 +935,12 @@ enum a5xx_tex_type {
|
|||
|
||||
#define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c
|
||||
|
||||
#define REG_A5XX_CP_ME_NRT_ADDR_LO 0x0000080d
|
||||
|
||||
#define REG_A5XX_CP_ME_NRT_ADDR_HI 0x0000080e
|
||||
|
||||
#define REG_A5XX_CP_ME_NRT_DATA 0x00000810
|
||||
|
||||
#define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817
|
||||
|
||||
#define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818
|
||||
|
|
@ -2110,9 +2116,17 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
|
|||
|
||||
#define REG_A5XX_PC_MODE_CNTL 0x00000d02
|
||||
|
||||
#define REG_A5XX_UNKNOWN_0D08 0x00000d08
|
||||
#define REG_A5XX_PC_INDEX_BUF_LO 0x00000d04
|
||||
|
||||
#define REG_A5XX_UNKNOWN_0D09 0x00000d09
|
||||
#define REG_A5XX_PC_INDEX_BUF_HI 0x00000d05
|
||||
|
||||
#define REG_A5XX_PC_START_INDEX 0x00000d06
|
||||
|
||||
#define REG_A5XX_PC_MAX_INDEX 0x00000d07
|
||||
|
||||
#define REG_A5XX_PC_TESSFACTOR_ADDR_LO 0x00000d08
|
||||
|
||||
#define REG_A5XX_PC_TESSFACTOR_ADDR_HI 0x00000d09
|
||||
|
||||
#define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10
|
||||
|
||||
|
|
@ -2739,7 +2753,7 @@ static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
|
|||
return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E093 0x0000e093
|
||||
#define REG_A5XX_GRAS_SU_LAYERED 0x0000e093
|
||||
|
||||
#define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
|
||||
#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
|
||||
|
|
@ -3709,6 +3723,7 @@ static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
|
|||
return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
|
||||
}
|
||||
#define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART 0x00000100
|
||||
#define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES 0x00000200
|
||||
#define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400
|
||||
|
||||
#define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
|
||||
|
|
@ -3733,11 +3748,43 @@ static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su
|
|||
|
||||
#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E38D 0x0000e38d
|
||||
#define REG_A5XX_PC_GS_LAYERED 0x0000e38d
|
||||
|
||||
#define REG_A5XX_PC_GS_PARAM 0x0000e38e
|
||||
#define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
|
||||
#define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
|
||||
static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A5XX_PC_GS_PARAM_MAX_VERTICES__MASK;
|
||||
}
|
||||
#define A5XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
|
||||
#define A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
|
||||
static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A5XX_PC_GS_PARAM_INVOCATIONS__MASK;
|
||||
}
|
||||
#define A5XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
|
||||
#define A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
|
||||
static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
|
||||
{
|
||||
return ((val) << A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A5XX_PC_GS_PARAM_PRIMTYPE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_PC_HS_PARAM 0x0000e38f
|
||||
#define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
|
||||
#define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
|
||||
static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A5XX_PC_HS_PARAM_VERTICES_OUT__MASK;
|
||||
}
|
||||
#define A5XX_PC_HS_PARAM_SPACING__MASK 0x00600000
|
||||
#define A5XX_PC_HS_PARAM_SPACING__SHIFT 21
|
||||
static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
|
||||
{
|
||||
return ((val) << A5XX_PC_HS_PARAM_SPACING__SHIFT) & A5XX_PC_HS_PARAM_SPACING__MASK;
|
||||
}
|
||||
#define A5XX_PC_HS_PARAM_CW 0x00800000
|
||||
#define A5XX_PC_HS_PARAM_CONNECTED 0x01000000
|
||||
|
||||
#define REG_A5XX_PC_POWER_CNTL 0x0000e3b0
|
||||
|
||||
|
|
@ -3762,10 +3809,40 @@ static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
|
|||
{
|
||||
return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
|
||||
}
|
||||
#define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
|
||||
#define A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
|
||||
static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_VFD_CONTROL_2 0x0000e402
|
||||
#define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff
|
||||
#define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0
|
||||
static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_VFD_CONTROL_3 0x0000e403
|
||||
#define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00
|
||||
#define A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8
|
||||
static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
|
||||
}
|
||||
#define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
|
||||
#define A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
|
||||
static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSX__MASK;
|
||||
}
|
||||
#define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
|
||||
#define A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
|
||||
static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSY__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_VFD_CONTROL_4 0x0000e404
|
||||
|
||||
|
|
@ -4108,12 +4185,6 @@ static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
|
|||
|
||||
#define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2
|
||||
|
||||
#define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3
|
||||
|
||||
#define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
|
||||
|
||||
#define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0
|
||||
#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008
|
||||
#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3
|
||||
|
|
@ -4142,6 +4213,12 @@ static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|||
return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2
|
||||
|
||||
#define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3
|
||||
|
||||
#define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E600 0x0000e600
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E602 0x0000e602
|
||||
|
|
@ -4571,6 +4648,8 @@ static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
|
|||
|
||||
#define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd
|
||||
|
||||
#define REG_A5XX_RB_2D_BLIT_CNTL 0x00002100
|
||||
|
||||
#define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101
|
||||
|
||||
#define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102
|
||||
|
|
@ -4586,12 +4665,19 @@ static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
|
|||
{
|
||||
return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK;
|
||||
}
|
||||
#define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
|
||||
#define A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT 8
|
||||
static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
|
||||
{
|
||||
return ((val) << A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK;
|
||||
}
|
||||
#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
|
||||
#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
|
||||
static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
||||
{
|
||||
return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
|
||||
}
|
||||
#define A5XX_RB_2D_SRC_INFO_FLAGS 0x00001000
|
||||
|
||||
#define REG_A5XX_RB_2D_SRC_LO 0x00002108
|
||||
|
||||
|
|
@ -4620,12 +4706,19 @@ static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
|
|||
{
|
||||
return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
|
||||
}
|
||||
#define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
|
||||
#define A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
|
||||
static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
|
||||
{
|
||||
return ((val) << A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_DST_INFO_TILE_MODE__MASK;
|
||||
}
|
||||
#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
|
||||
#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
|
||||
static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
||||
{
|
||||
return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
|
||||
}
|
||||
#define A5XX_RB_2D_DST_INFO_FLAGS 0x00001000
|
||||
|
||||
#define REG_A5XX_RB_2D_DST_LO 0x00002111
|
||||
|
||||
|
|
@ -4655,6 +4748,8 @@ static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
|
|||
|
||||
#define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
|
||||
|
||||
#define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180
|
||||
|
||||
#define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
|
||||
#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
|
||||
#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
|
||||
|
|
@ -4662,12 +4757,19 @@ static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt va
|
|||
{
|
||||
return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
|
||||
#define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT 8
|
||||
static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
|
||||
{
|
||||
return ((val) << A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
|
||||
#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
|
||||
static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
||||
{
|
||||
return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_2D_SRC_INFO_FLAGS 0x00001000
|
||||
|
||||
#define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
|
||||
#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
|
||||
|
|
@ -4676,12 +4778,19 @@ static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt va
|
|||
{
|
||||
return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK 0x00000300
|
||||
#define A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT 8
|
||||
static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
|
||||
{
|
||||
return ((val) << A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
|
||||
#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10
|
||||
static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
||||
{
|
||||
return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_2D_DST_INFO_FLAGS 0x00001000
|
||||
|
||||
#define REG_A5XX_UNKNOWN_2100 0x00002100
|
||||
|
||||
|
|
|
|||
|
|
@ -959,8 +959,8 @@ t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
|
|||
OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
|
||||
OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
|
||||
|
||||
OUT_PKT4(ring, REG_A5XX_UNKNOWN_E093, 1);
|
||||
OUT_RING(ring, 0x00000000); /* UNKNOWN_E093 */
|
||||
OUT_PKT4(ring, REG_A5XX_GRAS_SU_LAYERED, 1);
|
||||
OUT_RING(ring, 0x00000000); /* GRAS_SU_LAYERED */
|
||||
|
||||
OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1);
|
||||
OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */
|
||||
|
|
@ -974,8 +974,8 @@ t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
|
|||
OUT_PKT4(ring, REG_A5XX_UNKNOWN_E389, 1);
|
||||
OUT_RING(ring, 0x00000000); /* UNKNOWN_E389 */
|
||||
|
||||
OUT_PKT4(ring, REG_A5XX_UNKNOWN_E38D, 1);
|
||||
OUT_RING(ring, 0x00000000); /* UNKNOWN_E38D */
|
||||
OUT_PKT4(ring, REG_A5XX_PC_GS_LAYERED, 1);
|
||||
OUT_RING(ring, 0x00000000); /* PC_GS_LAYERED */
|
||||
|
||||
OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
|
||||
OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
|
||||
|
|
|
|||
|
|
@ -11,11 +11,11 @@ The rules-ng-ng source files this header was generated from are:
|
|||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 33379 bytes, from 2017-11-14 21:00:47)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13612 bytes, from 2017-11-28 14:06:11)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 34499 bytes, from 2017-12-17 17:36:55)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 143420 bytes, from 2017-11-16 20:29:34)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2017-11-28 14:06:11)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 145953 bytes, from 2017-12-17 17:36:55)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
|
|
@ -44,6 +44,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
*/
|
||||
|
||||
|
||||
enum chip {
|
||||
A2XX = 0,
|
||||
A3XX = 0,
|
||||
A4XX = 0,
|
||||
A5XX = 0,
|
||||
};
|
||||
|
||||
enum adreno_pa_su_sc_draw {
|
||||
PC_DRAW_POINTS = 0,
|
||||
PC_DRAW_LINES = 1,
|
||||
|
|
@ -183,6 +190,12 @@ enum a3xx_rb_blend_opcode {
|
|||
BLEND_MAX_DST_SRC = 4,
|
||||
};
|
||||
|
||||
enum a4xx_tess_spacing {
|
||||
EQUAL_SPACING = 0,
|
||||
ODD_SPACING = 2,
|
||||
EVEN_SPACING = 3,
|
||||
};
|
||||
|
||||
#define REG_AXXX_CP_RB_BASE 0x000001c0
|
||||
|
||||
#define REG_AXXX_CP_RB_CNTL 0x000001c1
|
||||
|
|
|
|||
|
|
@ -8,15 +8,15 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/ilia/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-11-18 20:43:22)
|
||||
- /home/ilia/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-11 01:04:14)
|
||||
- /home/ilia/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2017-11-18 20:48:10)
|
||||
- /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 15292 bytes, from 2017-11-19 20:45:26)
|
||||
- /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 34349 bytes, from 2017-11-19 20:43:33)
|
||||
- /home/ilia/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-11-18 19:40:11)
|
||||
- /home/ilia/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112609 bytes, from 2017-11-19 04:47:10)
|
||||
- /home/ilia/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 143017 bytes, from 2017-11-19 04:05:11)
|
||||
- /home/ilia/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-11-07 21:10:25)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13612 bytes, from 2017-11-28 14:06:11)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 34499 bytes, from 2017-12-17 17:36:55)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2017-11-28 14:06:11)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 145953 bytes, from 2017-12-17 17:36:55)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
@ -225,6 +225,7 @@ enum adreno_pm4_type3_packets {
|
|||
IN_INCR_UPDT_STATE = 85,
|
||||
IN_INCR_UPDT_CONST = 86,
|
||||
IN_INCR_UPDT_INSTR = 87,
|
||||
PKT4 = 4,
|
||||
};
|
||||
|
||||
enum adreno_state_block {
|
||||
|
|
@ -301,6 +302,7 @@ enum render_mode_cmd {
|
|||
GMEM = 3,
|
||||
BLIT2D = 5,
|
||||
BLIT2DSCALE = 7,
|
||||
END2D = 8,
|
||||
};
|
||||
|
||||
enum cp_blit_cmd {
|
||||
|
|
@ -1182,13 +1184,13 @@ static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
|
|||
}
|
||||
|
||||
#define REG_CP_BLIT_1 0x00000001
|
||||
#define CP_BLIT_1_SRC_X1__MASK 0x0000ffff
|
||||
#define CP_BLIT_1_SRC_X1__MASK 0x00003fff
|
||||
#define CP_BLIT_1_SRC_X1__SHIFT 0
|
||||
static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
|
||||
}
|
||||
#define CP_BLIT_1_SRC_Y1__MASK 0xffff0000
|
||||
#define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000
|
||||
#define CP_BLIT_1_SRC_Y1__SHIFT 16
|
||||
static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
|
||||
{
|
||||
|
|
@ -1196,13 +1198,13 @@ static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_CP_BLIT_2 0x00000002
|
||||
#define CP_BLIT_2_SRC_X2__MASK 0x0000ffff
|
||||
#define CP_BLIT_2_SRC_X2__MASK 0x00003fff
|
||||
#define CP_BLIT_2_SRC_X2__SHIFT 0
|
||||
static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
|
||||
}
|
||||
#define CP_BLIT_2_SRC_Y2__MASK 0xffff0000
|
||||
#define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000
|
||||
#define CP_BLIT_2_SRC_Y2__SHIFT 16
|
||||
static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
|
||||
{
|
||||
|
|
@ -1210,13 +1212,13 @@ static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_CP_BLIT_3 0x00000003
|
||||
#define CP_BLIT_3_DST_X1__MASK 0x0000ffff
|
||||
#define CP_BLIT_3_DST_X1__MASK 0x00003fff
|
||||
#define CP_BLIT_3_DST_X1__SHIFT 0
|
||||
static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
|
||||
}
|
||||
#define CP_BLIT_3_DST_Y1__MASK 0xffff0000
|
||||
#define CP_BLIT_3_DST_Y1__MASK 0x3fff0000
|
||||
#define CP_BLIT_3_DST_Y1__SHIFT 16
|
||||
static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
|
||||
{
|
||||
|
|
@ -1224,13 +1226,13 @@ static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_CP_BLIT_4 0x00000004
|
||||
#define CP_BLIT_4_DST_X2__MASK 0x0000ffff
|
||||
#define CP_BLIT_4_DST_X2__MASK 0x00003fff
|
||||
#define CP_BLIT_4_DST_X2__SHIFT 0
|
||||
static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
|
||||
}
|
||||
#define CP_BLIT_4_DST_Y2__MASK 0xffff0000
|
||||
#define CP_BLIT_4_DST_Y2__MASK 0x3fff0000
|
||||
#define CP_BLIT_4_DST_Y2__SHIFT 16
|
||||
static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue