From f1fe4d59612f250a2b184d6cf7e0a7bed07f13c0 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sun, 26 Jan 2025 15:37:40 +0100 Subject: [PATCH] etnaviv: replace open-coded shifts in shader range registers with macros Use the generated macros from the HW headers to do the shifting, which makes it more clear what is being done to those states. Signed-off-by: Lucas Stach Reviewed-by: Christian Gmeiner Part-of: --- src/gallium/drivers/etnaviv/etnaviv_emit.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c b/src/gallium/drivers/etnaviv/etnaviv_emit.c index 0bc635d6f10..d313c106163 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c @@ -675,7 +675,8 @@ etna_emit_state(struct etna_context *ctx) /* ICACHE (pre-HALTI5) */ assert(screen->specs.has_icache && screen->specs.has_unified_instmem); /* Set icache (VS) */ - etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16); + etna_set_state(stream, VIVS_VS_RANGE, + VIVS_VS_RANGE_HIGH(ctx->shader_state.vs_inst_mem_size / 4 - 1)); etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE | VIVS_VS_ICACHE_CONTROL_FLUSH_VS); @@ -683,7 +684,8 @@ etna_emit_state(struct etna_context *ctx) etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR); /* Set icache (PS) */ - etna_set_state(stream, VIVS_PS_RANGE, (ctx->shader_state.ps_inst_mem_size / 4 - 1) << 16); + etna_set_state(stream, VIVS_PS_RANGE, + VIVS_PS_RANGE_HIGH(ctx->shader_state.ps_inst_mem_size / 4 - 1)); etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE | VIVS_VS_ICACHE_CONTROL_FLUSH_PS); @@ -698,9 +700,11 @@ etna_emit_state(struct etna_context *ctx) VIVS_VS_ICACHE_CONTROL_FLUSH_VS); } if (screen->specs.has_unified_instmem) { - etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16); - etna_set_state(stream, VIVS_PS_RANGE, ((ctx->shader_state.ps_inst_mem_size / 4 - 1 + 0x100) << 16) | - 0x100); + etna_set_state(stream, VIVS_VS_RANGE, + VIVS_VS_RANGE_HIGH(ctx->shader_state.vs_inst_mem_size / 4 - 1)); + etna_set_state(stream, VIVS_PS_RANGE, + VIVS_PS_RANGE_HIGH(ctx->shader_state.ps_inst_mem_size / 4 - 1 + 0x100) | + VIVS_PS_RANGE_LOW(0x100)); } etna_set_state_multi(stream, screen->specs.vs_offset, ctx->shader_state.vs_inst_mem_size,