diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index d644ef8a171..9b42001cf18 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -289,6 +289,7 @@ isl_device_init(struct isl_device *dev,
    dev->info = info;
    dev->use_separate_stencil = ISL_GFX_VER(dev) >= 6;
    dev->has_bit6_swizzling = info->has_bit6_swizzle;
+   dev->buffer_length_in_aux_addr = false;
 
    /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
     * device properties at buildtime. Verify that the macros with the device
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 89da4d30d4e..928c70bd899 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1301,6 +1301,18 @@ struct isl_device {
       uint32_t protected_mask;
    } mocs;
 
+   /* Options to configure by the driver: */
+
+   /**
+    * Write buffer length in the upper dword of the
+    * RENDER_SURFACE_STATE::AuxilliarySurfaceBaseAddress field.
+    *
+    * This field is unused for buffer surfaces so we can reuse it store the
+    * buffer length. This is useful when you want to load a vec4 with (main
+    * address, size).
+    */
+   bool buffer_length_in_aux_addr;
+
    void (*surf_fill_state_s)(const struct isl_device *dev, void *state,
                              const struct isl_surf_fill_state_info *restrict info);
 
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index 396d57f313a..f5d9913d652 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -968,6 +968,17 @@ isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state,
    s.MOCS = info->mocs;
 #endif
 
+#if GFX_VER >= 9
+   /* Store the buffer size in the upper dword of the AUX surface base
+    * address. Only enabled on Gfx9+ since Gfx8 has an Atom version with only
+    * 32bits of address space.
+    */
+   if (dev->buffer_length_in_aux_addr)
+      s.AuxiliarySurfaceBaseAddress = info->size_B << 32;
+#else
+   assert(!dev->buffer_length_in_aux_addr);
+#endif
+
 #if GFX_VERx10 >= 125
    /* Setting L1 caching policy to Write-back mode. */
    s.L1CacheControl = L1CC_WB;