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gallium/radeon: remove old r600g code checking chip_class and family

Browse source 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-10-05 01:24:52 +02:00
parent c4ed39f85b
commit f1eb9a9c27
7 changed files with 52 additions and 225 deletions
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99
src/gallium/drivers/radeon/r600_pipe_common.c
View file

@ -104,7 +104,7 @@ void si_gfx_write_event_eop(struct r600_common_context *ctx,
/* Wait for write confirmation before writing data, but don't send
* an interrupt. */
if (ctx->chip_class >= SI && data_sel != EOP_DATA_SEL_DISCARD)
if (data_sel != EOP_DATA_SEL_DISCARD)
sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
if (ctx->chip_class >= GFX9) {
@ -292,12 +292,8 @@ static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
/* NOP waits for idle on Evergreen and later. */
if (rctx->chip_class >= CIK)
radeon_emit(cs, 0x00000000); /* NOP */
else if (rctx->chip_class >= EVERGREEN)
else
radeon_emit(cs, 0xf0000000); /* NOP */
else {
/* TODO: R600-R700 should use the FENCE packet.
* CS checker support is required. */
}
}
void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
@ -898,31 +894,6 @@ static const char *r600_get_marketing_name(struct radeon_winsys *ws)
static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
{
switch (rscreen->info.family) {
case CHIP_R600: return "AMD R600";
case CHIP_RV610: return "AMD RV610";
case CHIP_RV630: return "AMD RV630";
case CHIP_RV670: return "AMD RV670";
case CHIP_RV620: return "AMD RV620";
case CHIP_RV635: return "AMD RV635";
case CHIP_RS780: return "AMD RS780";
case CHIP_RS880: return "AMD RS880";
case CHIP_RV770: return "AMD RV770";
case CHIP_RV730: return "AMD RV730";
case CHIP_RV710: return "AMD RV710";
case CHIP_RV740: return "AMD RV740";
case CHIP_CEDAR: return "AMD CEDAR";
case CHIP_REDWOOD: return "AMD REDWOOD";
case CHIP_JUNIPER: return "AMD JUNIPER";
case CHIP_CYPRESS: return "AMD CYPRESS";
case CHIP_HEMLOCK: return "AMD HEMLOCK";
case CHIP_PALM: return "AMD PALM";
case CHIP_SUMO: return "AMD SUMO";
case CHIP_SUMO2: return "AMD SUMO2";
case CHIP_BARTS: return "AMD BARTS";
case CHIP_TURKS: return "AMD TURKS";
case CHIP_CAICOS: return "AMD CAICOS";
case CHIP_CAYMAN: return "AMD CAYMAN";
case CHIP_ARUBA: return "AMD ARUBA";
case CHIP_TAHITI: return "AMD TAHITI";
case CHIP_PITCAIRN: return "AMD PITCAIRN";
case CHIP_VERDE: return "AMD CAPE VERDE";
@ -1049,46 +1020,6 @@ static int r600_get_video_param(struct pipe_screen *screen,
const char *si_get_llvm_processor_name(enum radeon_family family)
{
switch (family) {
case CHIP_R600:
case CHIP_RV630:
case CHIP_RV635:
case CHIP_RV670:
return "r600";
case CHIP_RV610:
case CHIP_RV620:
case CHIP_RS780:
case CHIP_RS880:
return "rs880";
case CHIP_RV710:
return "rv710";
case CHIP_RV730:
return "rv730";
case CHIP_RV740:
case CHIP_RV770:
return "rv770";
case CHIP_PALM:
case CHIP_CEDAR:
return "cedar";
case CHIP_SUMO:
case CHIP_SUMO2:
return "sumo";
case CHIP_REDWOOD:
return "redwood";
case CHIP_JUNIPER:
return "juniper";
case CHIP_HEMLOCK:
case CHIP_CYPRESS:
return "cypress";
case CHIP_BARTS:
return "barts";
case CHIP_TURKS:
return "turks";
case CHIP_CAICOS:
return "caicos";
case CHIP_CAYMAN:
case CHIP_ARUBA:
return "cayman";
case CHIP_TAHITI: return "tahiti";
case CHIP_PITCAIRN: return "pitcairn";
case CHIP_VERDE: return "verde";
@ -1148,23 +1079,13 @@ static int r600_get_compute_param(struct pipe_screen *screen,
case PIPE_COMPUTE_CAP_IR_TARGET: {
const char *gpu;
const char *triple;
if (rscreen->family <= CHIP_ARUBA) {
triple = "r600--";
} else {
if (HAVE_LLVM < 0x0400) {
triple = "amdgcn--";
} else {
triple = "amdgcn-mesa-mesa3d";
}
}
switch(rscreen->family) {
/* Clang < 3.6 is missing Hainan in its list of
* GPUs, so we need to use the name of a similar GPU.
*/
default:
gpu = si_get_llvm_processor_name(rscreen->family);
break;
}
if (HAVE_LLVM < 0x0400)
triple = "amdgcn--";
else
triple = "amdgcn-mesa-mesa3d";
gpu = si_get_llvm_processor_name(rscreen->family);
if (ret) {
sprintf(ret, "%s-%s", gpu, triple);
}
@ -1280,7 +1201,7 @@ static int r600_get_compute_param(struct pipe_screen *screen,
case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
if (ret) {
uint32_t *subgroup_size = ret;
*subgroup_size = r600_wavefront_size(rscreen->family);
*subgroup_size = 64;
}
return sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:

20
src/gallium/drivers/radeon/r600_pipe_common.h
View file

@ -927,26 +927,6 @@ static inline unsigned r600_tex_aniso_filter(unsigned filter)
return 4;
}
static inline unsigned r600_wavefront_size(enum radeon_family family)
{
switch (family) {
case CHIP_RV610:
case CHIP_RS780:
case CHIP_RV620:
case CHIP_RS880:
return 16;
case CHIP_RV630:
case CHIP_RV635:
case CHIP_RV730:
case CHIP_RV710:
case CHIP_PALM:
case CHIP_CEDAR:
return 32;
default:
return 64;
}
}
static inline enum radeon_bo_priority
r600_get_sampler_view_priority(struct r600_resource *res)
{

31
src/gallium/drivers/radeon/r600_query.c
View file

@ -766,26 +766,17 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
emit_sample_streamout(cs, va + 32 * stream, stream);
break;
case PIPE_QUERY_TIME_ELAPSED:
if (ctx->chip_class >= SI) {
/* Write the timestamp from the CP not waiting for
* outstanding draws (top-of-pipe).
*/
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
radeon_emit(cs, COPY_DATA_COUNT_SEL |
COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC));
radeon_emit(cs, 0);
radeon_emit(cs, 0);
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
} else {
/* Write the timestamp after the last draw is done.
* (bottom-of-pipe)
*/
si_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
0, EOP_DATA_SEL_TIMESTAMP,
NULL, va, 0, query->b.type);
}
/* Write the timestamp from the CP not waiting for
* outstanding draws (top-of-pipe).
*/
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
radeon_emit(cs, COPY_DATA_COUNT_SEL |
COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC));
radeon_emit(cs, 0);
radeon_emit(cs, 0);
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));

96
src/gallium/drivers/radeon/r600_streamout.c
View file

@ -89,20 +89,10 @@ void si_streamout_buffers_dirty(struct r600_common_context *rctx)
num_bufs * 11; /* STRMOUT_BUFFER_UPDATE, BUFFER_SIZE */
begin->num_dw = 12; /* flush_vgt_streamout */
if (rctx->chip_class >= SI) {
begin->num_dw += num_bufs * 4; /* SET_CONTEXT_REG */
} else {
begin->num_dw += num_bufs * 7; /* SET_CONTEXT_REG */
if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740)
begin->num_dw += num_bufs * 5; /* STRMOUT_BASE_UPDATE */
}
begin->num_dw += num_bufs * 4; /* SET_CONTEXT_REG */
begin->num_dw +=
num_bufs_appended * 8 + /* STRMOUT_BUFFER_UPDATE */
(num_bufs - num_bufs_appended) * 6 + /* STRMOUT_BUFFER_UPDATE */
(rctx->family > CHIP_R600 && rctx->family < CHIP_RS780 ? 2 : 0); /* SURFACE_BASE_UPDATE */
(num_bufs - num_bufs_appended) * 6; + /* STRMOUT_BUFFER_UPDATE */
rctx->set_atom_dirty(rctx, begin, true);
@ -159,15 +149,9 @@ static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
/* The register is at different places on different ASICs. */
if (rctx->chip_class >= CIK) {
reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
} else if (rctx->chip_class >= EVERGREEN) {
reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
} else {
reg_strmout_cntl = R_008490_CP_STRMOUT_CNTL;
}
if (rctx->chip_class >= CIK) {
radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
} else {
reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
radeon_set_config_reg(cs, reg_strmout_cntl, 0);
}
@ -188,7 +172,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
struct radeon_winsys_cs *cs = rctx->gfx.cs;
struct r600_so_target **t = rctx->streamout.targets;
uint16_t *stride_in_dw = rctx->streamout.stride_in_dw;
unsigned i, update_flags = 0;
unsigned i;
r600_flush_vgt_streamout(rctx);
@ -198,39 +182,13 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
t[i]->stride_in_dw = stride_in_dw[i];
if (rctx->chip_class >= SI) {
/* SI binds streamout buffers as shader resources.
* VGT only counts primitives and tells the shader
* through SGPRs what to do. */
radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
radeon_emit(cs, (t[i]->b.buffer_offset +
t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
radeon_emit(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
} else {
uint64_t va = r600_resource(t[i]->b.buffer)->gpu_address;
update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
radeon_emit(cs, (t[i]->b.buffer_offset +
t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
radeon_emit(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
radeon_emit(cs, va >> 8); /* BUFFER_BASE */
r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RW_BUFFER);
/* R7xx requires this packet after updating BUFFER_BASE.
* Without this, R7xx locks up. */
if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740) {
radeon_emit(cs, PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0));
radeon_emit(cs, i);
radeon_emit(cs, va >> 8);
r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RW_BUFFER);
}
}
/* SI binds streamout buffers as shader resources.
* VGT only counts primitives and tells the shader
* through SGPRs what to do. */
radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
radeon_emit(cs, (t[i]->b.buffer_offset +
t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
radeon_emit(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
if (rctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
uint64_t va = t[i]->buf_filled_size->gpu_address +
@ -259,10 +217,6 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
}
}
if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
radeon_emit(cs, update_flags);
}
rctx->streamout.begin_emitted = true;
}
@ -315,24 +269,16 @@ void si_emit_streamout_end(struct r600_common_context *rctx)
static void r600_emit_streamout_enable(struct r600_common_context *rctx,
struct r600_atom *atom)
{
unsigned strmout_config_reg = R_028AB0_VGT_STRMOUT_EN;
unsigned strmout_config_val = S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx));
unsigned strmout_buffer_reg = R_028B20_VGT_STRMOUT_BUFFER_EN;
unsigned strmout_buffer_val = rctx->streamout.hw_enabled_mask &
rctx->streamout.enabled_stream_buffers_mask;
if (rctx->chip_class >= EVERGREEN) {
strmout_buffer_reg = R_028B98_VGT_STRMOUT_BUFFER_CONFIG;
strmout_config_reg = R_028B94_VGT_STRMOUT_CONFIG;
strmout_config_val |=
S_028B94_RAST_STREAM(0) |
S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx));
}
radeon_set_context_reg(rctx->gfx.cs, strmout_buffer_reg, strmout_buffer_val);
radeon_set_context_reg(rctx->gfx.cs, strmout_config_reg, strmout_config_val);
radeon_set_context_reg_seq(rctx->gfx.cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
radeon_emit(rctx->gfx.cs,
S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx)) |
S_028B94_RAST_STREAM(0) |
S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx)));
radeon_emit(rctx->gfx.cs,
rctx->streamout.hw_enabled_mask &
rctx->streamout.enabled_stream_buffers_mask);
}
static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable)

4
src/gallium/drivers/radeon/r600_texture.c
View file

@ -496,10 +496,6 @@ static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
templ.bind |= new_bind_flag;
/* r600g doesn't react to dirty_tex_descriptor_counter */
if (rctx->chip_class < SI)
return;
if (rtex->resource.b.is_shared)
return;

2
src/gallium/drivers/radeon/radeon_uvd.c
View file

@ -1358,7 +1358,7 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
switch(u_reduce_video_profile(templ->profile)) {
case PIPE_VIDEO_FORMAT_MPEG12:
if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM || info.family < CHIP_PALM)
if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
return vl_create_mpeg12_decoder(context, templ);
/* fall through */

25
src/gallium/drivers/radeon/radeon_video.c
View file

@ -261,8 +261,7 @@ int si_vid_get_video_param(struct pipe_screen *screen,
case PIPE_VIDEO_FORMAT_MPEG12:
return profile != PIPE_VIDEO_PROFILE_MPEG1;
case PIPE_VIDEO_FORMAT_MPEG4:
/* no support for MPEG4 on older hw */
return rscreen->family >= CHIP_PALM;
return 1;
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
if ((rscreen->family == CHIP_POLARIS10 ||
rscreen->family == CHIP_POLARIS11) &&
@ -305,21 +304,15 @@ int si_vid_get_video_param(struct pipe_screen *screen,
return PIPE_FORMAT_NV12;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
if (rscreen->family < CHIP_PALM) {
/* MPEG2 only with shaders and no support for
interlacing on R6xx style UVD */
return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
rscreen->family > CHIP_RV770;
} else {
enum pipe_video_format format = u_reduce_video_profile(profile);
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
enum pipe_video_format format = u_reduce_video_profile(profile);
if (format == PIPE_VIDEO_FORMAT_HEVC)
return false; //The firmware doesn't support interlaced HEVC.
else if (format == PIPE_VIDEO_FORMAT_JPEG)
return false;
return true;
}
if (format == PIPE_VIDEO_FORMAT_HEVC)
return false; //The firmware doesn't support interlaced HEVC.
else if (format == PIPE_VIDEO_FORMAT_JPEG)
return false;
return true;
}
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
return true;
case PIPE_VIDEO_CAP_MAX_LEVEL: