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anv/pipeline: Unify blend state setup between gen7 and gen8
This fixes all 674 broken dEQP-VK.pipeline.blend Vulkan CTS tests on
Haswell.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit a2e7b2e653)
This commit is contained in:
Jason Ekstrand
Emil Velikov
parent
cb9a2a4b85
commit
f194c84b37
3 changed files with 136 additions and 190 deletions
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@ -75,77 +75,6 @@ gen7_emit_rs_state(struct anv_pipeline *pipeline,
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GENX(3DSTATE_SF_pack)(NULL, &pipeline->gen7.sf, &sf);
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}
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static void
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gen7_emit_cb_state(struct anv_pipeline *pipeline,
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const VkPipelineColorBlendStateCreateInfo *info,
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const VkPipelineMultisampleStateCreateInfo *ms_info)
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{
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struct anv_device *device = pipeline->device;
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if (info == NULL || info->attachmentCount == 0) {
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pipeline->blend_state =
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anv_state_pool_emit(&device->dynamic_state_pool,
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GENX(BLEND_STATE), 64,
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.Entry = { {
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.ColorBufferBlendEnable = false,
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.WriteDisableAlpha = true,
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.WriteDisableRed = true,
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.WriteDisableGreen = true,
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.WriteDisableBlue = true
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} });
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} else {
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const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
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struct GENX(BLEND_STATE) blend = { .Entry = { {
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.AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
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.AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
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.LogicOpEnable = info->logicOpEnable,
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.LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
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.ColorBufferBlendEnable = a->blendEnable,
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.ColorClampRange = COLORCLAMP_RTFORMAT,
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.PreBlendColorClampEnable = true,
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.PostBlendColorClampEnable = true,
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.SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
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.DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
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.ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
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.SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
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.DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
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.AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
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.WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
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.WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
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.WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
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.WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
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} } };
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/* Our hardware applies the blend factor prior to the blend function
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* regardless of what function is used. Technically, this means the
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* hardware can do MORE than GL or Vulkan specify. However, it also
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* means that, for MIN and MAX, we have to stomp the blend factor to
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* ONE to make it a no-op.
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*/
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if (a->colorBlendOp == VK_BLEND_OP_MIN ||
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a->colorBlendOp == VK_BLEND_OP_MAX) {
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blend.Entry[0].SourceBlendFactor = BLENDFACTOR_ONE;
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blend.Entry[0].DestinationBlendFactor = BLENDFACTOR_ONE;
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}
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if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
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a->alphaBlendOp == VK_BLEND_OP_MAX) {
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blend.Entry[0].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
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blend.Entry[0].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
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}
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pipeline->blend_state = anv_state_pool_alloc(&device->dynamic_state_pool,
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GENX(BLEND_STATE_length) * 4,
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64);
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GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend);
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if (pipeline->device->info.has_llc)
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anv_state_clflush(pipeline->blend_state);
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}
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
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bsp.BlendStatePointer = pipeline->blend_state.offset;
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}
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}
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VkResult
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genX(graphics_pipeline_create)(
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VkDevice _device,
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@ -183,8 +112,8 @@ genX(graphics_pipeline_create)(
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emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
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gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
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pCreateInfo->pMultisampleState);
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emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
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pCreateInfo->pMultisampleState);
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emit_urb_setup(pipeline);
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@ -99,123 +99,6 @@ emit_rs_state(struct anv_pipeline *pipeline,
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GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);
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}
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static void
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emit_cb_state(struct anv_pipeline *pipeline,
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const VkPipelineColorBlendStateCreateInfo *info,
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const VkPipelineMultisampleStateCreateInfo *ms_info)
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{
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struct anv_device *device = pipeline->device;
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uint32_t num_dwords = GENX(BLEND_STATE_length);
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pipeline->blend_state =
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anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
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struct GENX(BLEND_STATE) blend_state = {
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.AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
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.AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
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};
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/* Default everything to disabled */
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for (uint32_t i = 0; i < 8; i++) {
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blend_state.Entry[i].WriteDisableAlpha = true;
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blend_state.Entry[i].WriteDisableRed = true;
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blend_state.Entry[i].WriteDisableGreen = true;
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blend_state.Entry[i].WriteDisableBlue = true;
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}
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struct anv_pipeline_bind_map *map =
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&pipeline->bindings[MESA_SHADER_FRAGMENT];
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bool has_writeable_rt = false;
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for (unsigned i = 0; i < map->surface_count; i++) {
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struct anv_pipeline_binding *binding = &map->surface_to_descriptor[i];
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/* All color attachments are at the beginning of the binding table */
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if (binding->set != ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS)
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break;
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/* We can have at most 8 attachments */
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assert(i < 8);
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if (binding->index >= info->attachmentCount)
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continue;
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assert(binding->binding == 0);
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const VkPipelineColorBlendAttachmentState *a =
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&info->pAttachments[binding->index];
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if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
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a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
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a->colorBlendOp != a->alphaBlendOp) {
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blend_state.IndependentAlphaBlendEnable = true;
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}
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blend_state.Entry[i] = (struct GENX(BLEND_STATE_ENTRY)) {
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.LogicOpEnable = info->logicOpEnable,
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.LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
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.ColorBufferBlendEnable = a->blendEnable,
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.PreBlendSourceOnlyClampEnable = false,
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.ColorClampRange = COLORCLAMP_RTFORMAT,
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.PreBlendColorClampEnable = true,
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.PostBlendColorClampEnable = true,
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.SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
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.DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
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.ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
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.SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
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.DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
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.AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
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.WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
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.WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
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.WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
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.WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
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};
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if (a->colorWriteMask != 0)
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has_writeable_rt = true;
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/* Our hardware applies the blend factor prior to the blend function
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* regardless of what function is used. Technically, this means the
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* hardware can do MORE than GL or Vulkan specify. However, it also
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* means that, for MIN and MAX, we have to stomp the blend factor to
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* ONE to make it a no-op.
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*/
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if (a->colorBlendOp == VK_BLEND_OP_MIN ||
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a->colorBlendOp == VK_BLEND_OP_MAX) {
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blend_state.Entry[i].SourceBlendFactor = BLENDFACTOR_ONE;
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blend_state.Entry[i].DestinationBlendFactor = BLENDFACTOR_ONE;
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}
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if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
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a->alphaBlendOp == VK_BLEND_OP_MAX) {
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blend_state.Entry[i].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
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blend_state.Entry[i].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
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}
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}
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struct GENX(BLEND_STATE_ENTRY) *bs0 = &blend_state.Entry[0];
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_BLEND), blend) {
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blend.AlphaToCoverageEnable = blend_state.AlphaToCoverageEnable;
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blend.HasWriteableRT = has_writeable_rt;
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blend.ColorBufferBlendEnable = bs0->ColorBufferBlendEnable;
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blend.SourceAlphaBlendFactor = bs0->SourceAlphaBlendFactor;
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blend.DestinationAlphaBlendFactor = bs0->DestinationAlphaBlendFactor;
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blend.SourceBlendFactor = bs0->SourceBlendFactor;
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blend.DestinationBlendFactor = bs0->DestinationBlendFactor;
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blend.AlphaTestEnable = false;
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blend.IndependentAlphaBlendEnable =
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blend_state.IndependentAlphaBlendEnable;
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}
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GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
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if (!device->info.has_llc)
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anv_state_clflush(pipeline->blend_state);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
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bsp.BlendStatePointer = pipeline->blend_state.offset;
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bsp.BlendStatePointerValid = true;
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}
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}
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static void
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emit_ms_state(struct anv_pipeline *pipeline,
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const VkPipelineMultisampleStateCreateInfo *info)
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@ -512,3 +512,137 @@ emit_ds_state(struct anv_pipeline *pipeline,
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GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, depth_stencil_dw, &depth_stencil);
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#endif
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}
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static void
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emit_cb_state(struct anv_pipeline *pipeline,
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const VkPipelineColorBlendStateCreateInfo *info,
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const VkPipelineMultisampleStateCreateInfo *ms_info)
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{
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struct anv_device *device = pipeline->device;
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const uint32_t num_dwords = GENX(BLEND_STATE_length);
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pipeline->blend_state =
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anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
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struct GENX(BLEND_STATE) blend_state = {
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#if GEN_GEN >= 8
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.AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
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.AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
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#else
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/* Make sure it gets zeroed */
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.Entry = { { 0, }, },
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#endif
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};
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/* Default everything to disabled */
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for (uint32_t i = 0; i < 8; i++) {
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blend_state.Entry[i].WriteDisableAlpha = true;
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blend_state.Entry[i].WriteDisableRed = true;
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blend_state.Entry[i].WriteDisableGreen = true;
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blend_state.Entry[i].WriteDisableBlue = true;
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}
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struct anv_pipeline_bind_map *map =
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&pipeline->bindings[MESA_SHADER_FRAGMENT];
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bool has_writeable_rt = false;
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for (unsigned i = 0; i < map->surface_count; i++) {
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struct anv_pipeline_binding *binding = &map->surface_to_descriptor[i];
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/* All color attachments are at the beginning of the binding table */
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if (binding->set != ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS)
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break;
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/* We can have at most 8 attachments */
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assert(i < 8);
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if (binding->index >= info->attachmentCount)
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continue;
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assert(binding->binding == 0);
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const VkPipelineColorBlendAttachmentState *a =
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&info->pAttachments[binding->index];
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blend_state.Entry[i] = (struct GENX(BLEND_STATE_ENTRY)) {
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#if GEN_GEN < 8
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.AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
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.AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
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#endif
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.LogicOpEnable = info->logicOpEnable,
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.LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
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.ColorBufferBlendEnable = a->blendEnable,
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.ColorClampRange = COLORCLAMP_RTFORMAT,
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.PreBlendColorClampEnable = true,
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.PostBlendColorClampEnable = true,
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.SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
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.DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
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.ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
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.SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
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.DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
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.AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
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.WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
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.WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
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.WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
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.WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
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};
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if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
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a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
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a->colorBlendOp != a->alphaBlendOp) {
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#if GEN_GEN >= 8
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blend_state.IndependentAlphaBlendEnable = true;
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#else
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blend_state.Entry[i].IndependentAlphaBlendEnable = true;
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#endif
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}
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if (a->colorWriteMask != 0)
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has_writeable_rt = true;
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/* Our hardware applies the blend factor prior to the blend function
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* regardless of what function is used. Technically, this means the
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* hardware can do MORE than GL or Vulkan specify. However, it also
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* means that, for MIN and MAX, we have to stomp the blend factor to
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* ONE to make it a no-op.
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*/
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if (a->colorBlendOp == VK_BLEND_OP_MIN ||
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a->colorBlendOp == VK_BLEND_OP_MAX) {
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blend_state.Entry[i].SourceBlendFactor = BLENDFACTOR_ONE;
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blend_state.Entry[i].DestinationBlendFactor = BLENDFACTOR_ONE;
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}
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if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
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a->alphaBlendOp == VK_BLEND_OP_MAX) {
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blend_state.Entry[i].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
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blend_state.Entry[i].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
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}
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}
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#if GEN_GEN >= 8
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struct GENX(BLEND_STATE_ENTRY) *bs0 = &blend_state.Entry[0];
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_BLEND), blend) {
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blend.AlphaToCoverageEnable = blend_state.AlphaToCoverageEnable;
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blend.HasWriteableRT = has_writeable_rt;
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blend.ColorBufferBlendEnable = bs0->ColorBufferBlendEnable;
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blend.SourceAlphaBlendFactor = bs0->SourceAlphaBlendFactor;
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blend.DestinationAlphaBlendFactor = bs0->DestinationAlphaBlendFactor;
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blend.SourceBlendFactor = bs0->SourceBlendFactor;
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blend.DestinationBlendFactor = bs0->DestinationBlendFactor;
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blend.AlphaTestEnable = false;
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blend.IndependentAlphaBlendEnable =
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blend_state.IndependentAlphaBlendEnable;
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}
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#else
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(void)has_writeable_rt;
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#endif
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GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
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if (!device->info.has_llc)
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anv_state_clflush(pipeline->blend_state);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
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bsp.BlendStatePointer = pipeline->blend_state.offset;
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#if GEN_GEN >= 8
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bsp.BlendStatePointerValid = true;
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#endif
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}
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}
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