From f182b1952af269a6514835ef8ed6a6dfc98f7bfb Mon Sep 17 00:00:00 2001 From: Timothy Arceri Date: Wed, 10 Aug 2022 12:14:07 +1000 Subject: [PATCH] glsl: remove GLSL IR inverse comparison optimisations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As per 7d85dc4f350b GLSL IR is not smart enough to handle this correctly for NANs. Shader-db radeonsi (RX 6800): Totals from affected shaders: SGPRS: 26848 -> 26848 (0.00 %) VGPRS: 13552 -> 13552 (0.00 %) Spilled SGPRs: 134 -> 134 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 635000 -> 630988 (-0.63 %) bytes Max Waves: 5474 -> 5474 (0.00 %) Shader-db iris (BDW): total instructions in shared programs: 17538859 -> 17539018 (<.01%) instructions in affected programs: 29369 -> 29528 (0.54%) helped: 3 HURT: 126 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 0.49% max: 0.49% x̄: 0.49% x̃: 0.49% HURT stats (abs) min: 1 max: 2 x̄: 1.29 x̃: 1 HURT stats (rel) min: 0.27% max: 1.32% x̄: 0.61% x̃: 0.54% 95% mean confidence interval for instructions value: 1.13 1.33 95% mean confidence interval for instructions %-change: 0.54% 0.63% Instructions are HURT. total loops in shared programs: 4866 -> 4866 (0.00%) loops in affected programs: 0 -> 0 helped: 0 HURT: 0 total cycles in shared programs: 858548230 -> 858548915 (<.01%) cycles in affected programs: 1331737 -> 1332422 (0.05%) helped: 0 HURT: 92 HURT stats (abs) min: 2 max: 49 x̄: 7.45 x̃: 6 HURT stats (rel) min: 0.01% max: 1.90% x̄: 0.12% x̃: 0.05% 95% mean confidence interval for cycles value: 5.72 9.17 95% mean confidence interval for cycles %-change: 0.05% 0.19% Cycles are HURT. Note: With the addition of "nir/comparison_pre: See through an inot to apply the optimization", idr's shader-db results are: All Broadwell and newer Intel platforms had similar results. (Ice Lake shown) total instructions in shared programs: 19940805 -> 19940802 (<.01%) instructions in affected programs: 582 -> 579 (-0.52%) helped: 3 / HURT: 0 total cycles in shared programs: 858431633 -> 858431747 (<.01%) cycles in affected programs: 4938 -> 5052 (2.31%) helped: 0 / HURT: 3 All older Intel platforms had similar results. (Haswell shown) total instructions in shared programs: 16715626 -> 16715670 (<.01%) instructions in affected programs: 9496 -> 9540 (0.46%) helped: 0 / HURT: 44 total cycles in shared programs: 881224396 -> 881232314 (<.01%) cycles in affected programs: 600610 -> 608528 (1.32%) helped: 6 / HURT: 44 Reviewed-by: Ian Romanick Part-of: --- src/compiler/glsl/opt_algebraic.cpp | 30 ----------------------------- 1 file changed, 30 deletions(-) diff --git a/src/compiler/glsl/opt_algebraic.cpp b/src/compiler/glsl/opt_algebraic.cpp index 8bf93c14848..4f093a2398a 100644 --- a/src/compiler/glsl/opt_algebraic.cpp +++ b/src/compiler/glsl/opt_algebraic.cpp @@ -431,36 +431,6 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir) } break; - case ir_unop_logic_not: { - enum ir_expression_operation new_op = ir_unop_logic_not; - - if (op_expr[0] == NULL) - break; - - switch (op_expr[0]->operation) { - case ir_binop_less: new_op = ir_binop_gequal; break; - case ir_binop_gequal: new_op = ir_binop_less; break; - case ir_binop_equal: new_op = ir_binop_nequal; break; - case ir_binop_nequal: new_op = ir_binop_equal; break; - case ir_binop_all_equal: new_op = ir_binop_any_nequal; break; - case ir_binop_any_nequal: new_op = ir_binop_all_equal; break; - - default: - /* The default case handler is here to silence a warning from GCC. - */ - break; - } - - if (new_op != ir_unop_logic_not) { - return new(mem_ctx) ir_expression(new_op, - ir->type, - op_expr[0]->operands[0], - op_expr[0]->operands[1]); - } - - break; - } - case ir_unop_saturate: if (op_expr[0] && op_expr[0]->operation == ir_binop_add) { ir_expression *b2f_0 = op_expr[0]->operands[0]->as_expression();