radeonsi: fix video processing path without VPE enabled

Fixes: 6b441ef6ab (amd, radeonsi: supports post processing entrypoint)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10495
Cc: mesa-stable

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27339>
(cherry picked from commit 46f5a226d6)
This commit is contained in:
Leo Liu 2024-01-29 12:25:44 -05:00 committed by Eric Engestrom
parent d2064c52fb
commit f135adb82a
3 changed files with 6 additions and 8 deletions

View file

@ -854,7 +854,7 @@
"description": "radeonsi: fix video processing path without VPE enabled",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "6b441ef6ab1e89da5560cd31711feb499a9cd8ff",
"notes": null

View file

@ -575,12 +575,9 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
/* Return the capability of Video Post Processor.
* Have to determine the HW version of VPE.
* Have to check the HW limitation and
* Check if the VPE exists and is valid
*/
if (entrypoint == PIPE_VIDEO_ENTRYPOINT_PROCESSING) {
/* Check if the VPE exists and is valid */
if (!sscreen->info.ip[AMD_IP_VPE].num_queues) {
return false;
}
if (sscreen->info.ip[AMD_IP_VPE].num_queues && entrypoint == PIPE_VIDEO_ENTRYPOINT_PROCESSING) {
switch(param) {
case PIPE_VIDEO_CAP_SUPPORTED:
@ -1011,7 +1008,7 @@ static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_for
{
struct si_screen *sscreen = (struct si_screen *)screen;
if (entrypoint == PIPE_VIDEO_ENTRYPOINT_PROCESSING) {
if (sscreen->info.ip[AMD_IP_VPE].num_queues && entrypoint == PIPE_VIDEO_ENTRYPOINT_PROCESSING) {
/* Todo:
* Unable to confirm whether it is asking for an input or output type
* Have to modify va frontend for solving this problem

View file

@ -115,7 +115,8 @@ struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
else
return si_vce_create_encoder(context, templ, ctx->ws, si_vce_get_buffer);
}
} else if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_PROCESSING)
} else if (((struct si_screen *)(context->screen))->info.ip[AMD_IP_VPE].num_queues &&
templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_PROCESSING)
return si_vpe_create_processor(context, templ);
if (ctx->vcn_ip_ver == VCN_4_0_0)