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i965: Introduce an OUT_RELOC64 macro.

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Broadwell uses 48-bit addresses.  The first DWord is the low 32 bits,
and the second DWord is the high 16 bits.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
This commit is contained in:
Kenneth Graunke 2013-11-04 16:55:26 -08:00
parent 67ebcb4711
commit f11c1feaf7
2 changed files with 34 additions and 0 deletions
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24
src/mesa/drivers/dri/i965/intel_batchbuffer.c
View file

@ -397,6 +397,30 @@ intel_batchbuffer_emit_reloc(struct brw_context *brw,
return true; return true;
} }
bool
intel_batchbuffer_emit_reloc64(struct brw_context *brw,
drm_intel_bo *buffer,
uint32_t read_domains, uint32_t write_domain,
uint32_t delta)
{
int ret = drm_intel_bo_emit_reloc(brw->batch.bo, 4*brw->batch.used,
buffer, delta,
read_domains, write_domain);
assert(ret == 0);
(void) ret;
/* Using the old buffer offset, write in what the right data would be, in
* case the buffer doesn't move and we can short-circuit the relocation
* processing in the kernel
*/
uint64_t offset = buffer->offset64 + delta;
intel_batchbuffer_emit_dword(brw, offset);
intel_batchbuffer_emit_dword(brw, offset >> 32);
return true;
}
void void
intel_batchbuffer_data(struct brw_context *brw, intel_batchbuffer_data(struct brw_context *brw,
const void *data, GLuint bytes, enum brw_gpu_ring ring) const void *data, GLuint bytes, enum brw_gpu_ring ring)

10
src/mesa/drivers/dri/i965/intel_batchbuffer.h
View file

@ -59,6 +59,11 @@ bool intel_batchbuffer_emit_reloc(struct brw_context *brw,
uint32_t read_domains, uint32_t read_domains,
uint32_t write_domain, uint32_t write_domain,
uint32_t offset); uint32_t offset);
bool intel_batchbuffer_emit_reloc64(struct brw_context *brw,
drm_intel_bo *buffer,
uint32_t read_domains,
uint32_t write_domain,
uint32_t offset);
void intel_batchbuffer_emit_mi_flush(struct brw_context *brw); void intel_batchbuffer_emit_mi_flush(struct brw_context *brw);
void intel_emit_post_sync_nonzero_flush(struct brw_context *brw); void intel_emit_post_sync_nonzero_flush(struct brw_context *brw);
void intel_emit_depth_stall_flushes(struct brw_context *brw); void intel_emit_depth_stall_flushes(struct brw_context *brw);
@ -167,6 +172,11 @@ intel_batchbuffer_advance(struct brw_context *brw)
read_domains, write_domain, delta); \ read_domains, write_domain, delta); \
} while (0) } while (0)
/* Handle 48-bit address relocations for Gen8+ */
#define OUT_RELOC64(buf, read_domains, write_domain, delta) do { \
intel_batchbuffer_emit_reloc64(brw, buf, read_domains, write_domain, delta); \
} while (0)
#define ADVANCE_BATCH() intel_batchbuffer_advance(brw); #define ADVANCE_BATCH() intel_batchbuffer_advance(brw);
#ifdef __cplusplus #ifdef __cplusplus