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nvc0: update/fix supported instruction src modifiers

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This commit is contained in:
Christoph Bumiller 2011-03-05 22:24:57 +01:00
parent dedc81e1dc
commit f10b2021c1
5 changed files with 31 additions and 20 deletions
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8
src/gallium/drivers/nvc0/nvc0_pc.c
View file

@ -25,6 +25,14 @@
#include "nvc0_pc.h"
#include "nvc0_program.h"
uint8_t
nvc0_ir_reverse_cc(uint8_t cc)
{
static const uint8_t cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
return cc_swapped[cc & 7] | (cc & ~7);
}
boolean
nvc0_insn_can_load(struct nv_instruction *nvi, int s,
struct nv_instruction *ld)

14
src/gallium/drivers/nvc0/nvc0_pc.h
View file

@ -210,6 +210,8 @@
#define NV_CC_P 0
#define NV_CC_NOT_P 1
uint8_t nvc0_ir_reverse_cc(uint8_t cc);
#define NV_PC_MAX_INSTRUCTIONS 2048
#define NV_PC_MAX_VALUES (NV_PC_MAX_INSTRUCTIONS * 4)
@ -219,7 +221,7 @@ struct nv_op_info {
uint base; /* e.g. ADD_S32 -> ADD */
char name[12];
uint8_t type;
uint8_t mods;
uint16_t mods;
unsigned flow : 1;
unsigned commutative : 1;
unsigned vector : 1;
@ -234,12 +236,6 @@ extern struct nv_op_info nvc0_op_info_table[];
#define NV_BASEOP(op) (nvc0_op_info_table[op].base)
#define NV_OPTYPE(op) (nvc0_op_info_table[op].type)
static INLINE uint
nv_op_base(uint opcode)
{
return nvc0_op_info_table[opcode].base;
}
static INLINE boolean
nv_is_texture_op(uint opcode)
{
@ -259,9 +255,9 @@ nv_op_commutative(uint opcode)
}
static INLINE uint8_t
nv_op_supported_src_mods(uint opcode)
nv_op_supported_src_mods(uint opcode, int s)
{
return nvc0_op_info_table[opcode].mods;
return (nvc0_op_info_table[opcode].mods >> (s * 4)) & 0xf;
}
static INLINE uint

7
src/gallium/drivers/nvc0/nvc0_pc_emit.c
View file

@ -610,6 +610,8 @@ emit_selp(struct nv_pc *pc, struct nv_instruction *i)
static void
emit_slct(struct nv_pc *pc, struct nv_instruction *i)
{
uint8_t cc = i->set_cond;
pc->emit[0] = 0x00000000;
switch (i->opcode) {
@ -627,7 +629,10 @@ emit_slct(struct nv_pc *pc, struct nv_instruction *i)
emit_form_0(pc, i);
pc->emit[1] |= i->set_cond << 23;
if (i->src[2]->mod & NV_MOD_NEG)
cc = nvc0_ir_reverse_cc(cc);
pc->emit[1] |= cc << 23;
}
static void

6
src/gallium/drivers/nvc0/nvc0_pc_optimize.c
View file

@ -240,8 +240,6 @@ is_immd32_load(struct nv_instruction *nvi)
static INLINE void
check_swap_src_0_1(struct nv_instruction *nvi)
{
static const uint8_t cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
struct nv_ref *src0 = nvi->src[0];
struct nv_ref *src1 = nvi->src[1];
@ -270,7 +268,7 @@ check_swap_src_0_1(struct nv_instruction *nvi)
if (nvi->src[0] != src0) {
if (NV_BASEOP(nvi->opcode) == NV_OP_SET)
nvi->set_cond = (nvi->set_cond & ~7) | cc_swapped[nvi->set_cond & 7];
nvi->set_cond = nvc0_ir_reverse_cc(nvi->set_cond);
else
if (NV_BASEOP(nvi->opcode) == NV_OP_SLCT)
nvi->set_cond = NV_CC_INVERSE(nvi->set_cond);
@ -363,7 +361,7 @@ nv_pass_lower_mods(struct nv_pass *ctx, struct nv_basic_block *b)
mod = 0;
}
if ((nv_op_supported_src_mods(nvi->opcode) & mod) != mod)
if ((nv_op_supported_src_mods(nvi->opcode, j) & mod) != mod)
continue;
nv_reference(ctx->pc, nvi, j, mi->src[0]->value);

16
src/gallium/drivers/nvc0/nvc0_pc_print.c
View file

@ -269,7 +269,11 @@ nvc0_print_instruction(struct nv_instruction *i)
PRINT(" %s\n", norm);
}
#define NV_MOD_SGN NV_MOD_ABS | NV_MOD_NEG
#define NV_MOD_SGN_12 ((NV_MOD_ABS | NV_MOD_NEG) | ((NV_MOD_ABS | NV_MOD_NEG) << 4))
#define NV_MOD_NEG_123 (NV_MOD_NEG | (NV_MOD_NEG << 4) | (NV_MOD_NEG << 8))
#define NV_MOD_NEG_3 (NV_MOD_NEG << 8)
#define NV_MOD_SGN NV_MOD_SGN_12
struct nv_op_info nvc0_op_info_table[NV_OP_COUNT + 1] =
{
@ -292,8 +296,8 @@ struct nv_op_info nvc0_op_info_table[NV_OP_COUNT + 1] =
{ NV_OP_SET, "set", NV_TYPE_ANY, NV_MOD_SGN, 0, 0, 0, 1, 0, 0, 0 },
{ NV_OP_ADD, "add", NV_TYPE_F32, NV_MOD_SGN, 0, 1, 0, 1, 0, 2, 2 },
{ NV_OP_SUB, "sub", NV_TYPE_F32, NV_MOD_SGN, 0, 0, 0, 1, 0, 2, 2 },
{ NV_OP_MUL, "mul", NV_TYPE_F32, NV_MOD_SGN, 0, 1, 0, 1, 0, 2, 2 },
{ NV_OP_MAD, "mad", NV_TYPE_F32, NV_MOD_SGN, 0, 1, 0, 1, 0, 2, 2 },
{ NV_OP_MUL, "mul", NV_TYPE_F32, NV_MOD_NEG_123, 0, 1, 0, 1, 0, 2, 2 },
{ NV_OP_MAD, "mad", NV_TYPE_F32, NV_MOD_NEG_123, 0, 1, 0, 1, 0, 2, 2 },
{ NV_OP_ABS, "abs", NV_TYPE_F32, 0, 0, 0, 0, 1, 0, 0, 0 },
{ NV_OP_NEG, "neg", NV_TYPE_F32, NV_MOD_ABS, 0, 0, 0, 1, 0, 0, 0 },
{ NV_OP_MAX, "max", NV_TYPE_F32, NV_MOD_SGN, 0, 1, 0, 1, 0, 2, 2 },
@ -363,9 +367,9 @@ struct nv_op_info nvc0_op_info_table[NV_OP_COUNT + 1] =
{ NV_OP_SELP, "selp", NV_TYPE_U32, 0, 0, 0, 0, 1, 0, 0, 0 },
{ NV_OP_SLCT, "slct", NV_TYPE_F32, 0, 0, 0, 0, 1, 0, 2, 2 },
{ NV_OP_SLCT, "slct", NV_TYPE_S32, 0, 0, 0, 0, 1, 0, 2, 2 },
{ NV_OP_SLCT, "slct", NV_TYPE_U32, 0, 0, 0, 0, 1, 0, 2, 2 },
{ NV_OP_SLCT, "slct", NV_TYPE_F32, NV_MOD_NEG_3, 0, 0, 0, 1, 0, 2, 2 },
{ NV_OP_SLCT, "slct", NV_TYPE_S32, NV_MOD_NEG_3, 0, 0, 0, 1, 0, 2, 2 },
{ NV_OP_SLCT, "slct", NV_TYPE_U32, NV_MOD_NEG_3, 0, 0, 0, 1, 0, 2, 2 },
{ NV_OP_ADD, "sub", NV_TYPE_F32, 0, 0, 0, 0, 1, 0, 1, 0 },