mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-26 17:10:11 +01:00
i965: Remove tabs from instruction scheduler.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Matt Turner
parent
51f7f613f9
commit
f0fa6a5e86
1 changed files with 97 additions and 97 deletions
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@ -673,7 +673,7 @@ instruction_scheduler::compute_delay(schedule_node *n)
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*/
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void
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instruction_scheduler::add_dep(schedule_node *before, schedule_node *after,
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int latency)
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int latency)
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{
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if (!before || !after)
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return;
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@ -682,22 +682,22 @@ instruction_scheduler::add_dep(schedule_node *before, schedule_node *after,
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for (int i = 0; i < before->child_count; i++) {
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if (before->children[i] == after) {
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before->child_latency[i] = MAX2(before->child_latency[i], latency);
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return;
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before->child_latency[i] = MAX2(before->child_latency[i], latency);
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return;
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}
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}
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if (before->child_array_size <= before->child_count) {
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if (before->child_array_size < 16)
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before->child_array_size = 16;
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before->child_array_size = 16;
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else
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before->child_array_size *= 2;
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before->child_array_size *= 2;
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before->children = reralloc(mem_ctx, before->children,
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schedule_node *,
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before->child_array_size);
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schedule_node *,
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before->child_array_size);
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before->child_latency = reralloc(mem_ctx, before->child_latency,
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int, before->child_array_size);
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int, before->child_array_size);
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}
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before->children[before->child_count] = after;
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@ -728,15 +728,15 @@ instruction_scheduler::add_barrier_deps(schedule_node *n)
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if (prev) {
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while (!prev->is_head_sentinel()) {
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add_dep(prev, n, 0);
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prev = (schedule_node *)prev->prev;
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add_dep(prev, n, 0);
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prev = (schedule_node *)prev->prev;
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}
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}
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if (next) {
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while (!next->is_tail_sentinel()) {
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add_dep(n, next, 0);
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next = (schedule_node *)next->next;
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add_dep(n, next, 0);
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next = (schedule_node *)next->next;
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}
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}
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}
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@ -791,7 +791,7 @@ fs_instruction_scheduler::calculate_deps()
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/* read-after-write deps. */
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for (int i = 0; i < inst->sources; i++) {
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if (inst->src[i].file == GRF) {
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if (inst->src[i].file == GRF) {
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if (post_reg_alloc) {
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for (int r = 0; r < inst->regs_read(v, i); r++)
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add_dep(last_grf_write[inst->src[i].reg + r], n);
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@ -800,10 +800,10 @@ fs_instruction_scheduler::calculate_deps()
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add_dep(last_grf_write[inst->src[i].reg * 16 + inst->src[i].reg_offset + r], n);
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}
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}
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} else if (inst->src[i].file == HW_REG &&
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(inst->src[i].fixed_hw_reg.file ==
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BRW_GENERAL_REGISTER_FILE)) {
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if (post_reg_alloc) {
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} else if (inst->src[i].file == HW_REG &&
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(inst->src[i].fixed_hw_reg.file ==
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BRW_GENERAL_REGISTER_FILE)) {
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if (post_reg_alloc) {
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int size = reg_width;
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if (inst->src[i].fixed_hw_reg.vstride == BRW_VERTICAL_STRIDE_0)
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size = 1;
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@ -814,28 +814,28 @@ fs_instruction_scheduler::calculate_deps()
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}
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} else if (inst->src[i].is_accumulator()) {
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add_dep(last_accumulator_write, n);
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} else if (inst->src[i].file != BAD_FILE &&
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inst->src[i].file != IMM &&
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inst->src[i].file != UNIFORM &&
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} else if (inst->src[i].file != BAD_FILE &&
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inst->src[i].file != IMM &&
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inst->src[i].file != UNIFORM &&
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(inst->src[i].file != HW_REG ||
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inst->src[i].fixed_hw_reg.file != IMM)) {
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assert(inst->src[i].file != MRF);
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add_barrier_deps(n);
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}
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assert(inst->src[i].file != MRF);
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add_barrier_deps(n);
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}
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}
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if (inst->base_mrf != -1) {
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for (int i = 0; i < inst->mlen; i++) {
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/* It looks like the MRF regs are released in the send
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* instruction once it's sent, not when the result comes
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* back.
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*/
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add_dep(last_mrf_write[inst->base_mrf + i], n);
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}
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for (int i = 0; i < inst->mlen; i++) {
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/* It looks like the MRF regs are released in the send
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* instruction once it's sent, not when the result comes
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* back.
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*/
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add_dep(last_mrf_write[inst->base_mrf + i], n);
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}
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}
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if (inst->reads_flag()) {
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add_dep(last_conditional_mod[inst->flag_subreg], n);
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add_dep(last_conditional_mod[inst->flag_subreg], n);
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}
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if (inst->reads_accumulator_implicitly()) {
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@ -856,20 +856,20 @@ fs_instruction_scheduler::calculate_deps()
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}
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}
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} else if (inst->dst.file == MRF) {
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int reg = inst->dst.reg & ~BRW_MRF_COMPR4;
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int reg = inst->dst.reg & ~BRW_MRF_COMPR4;
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add_dep(last_mrf_write[reg], n);
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last_mrf_write[reg] = n;
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if (is_compressed(inst)) {
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if (inst->dst.reg & BRW_MRF_COMPR4)
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reg += 4;
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else
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reg++;
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add_dep(last_mrf_write[reg], n);
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last_mrf_write[reg] = n;
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}
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add_dep(last_mrf_write[reg], n);
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last_mrf_write[reg] = n;
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if (is_compressed(inst)) {
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if (inst->dst.reg & BRW_MRF_COMPR4)
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reg += 4;
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else
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reg++;
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add_dep(last_mrf_write[reg], n);
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last_mrf_write[reg] = n;
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}
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} else if (inst->dst.file == HW_REG &&
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inst->dst.fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) {
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inst->dst.fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) {
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if (post_reg_alloc) {
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for (int r = 0; r < reg_width; r++)
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last_grf_write[inst->dst.fixed_hw_reg.nr + r] = n;
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@ -880,19 +880,19 @@ fs_instruction_scheduler::calculate_deps()
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add_dep(last_accumulator_write, n);
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last_accumulator_write = n;
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} else if (inst->dst.file != BAD_FILE) {
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add_barrier_deps(n);
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add_barrier_deps(n);
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}
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if (inst->mlen > 0 && inst->base_mrf != -1) {
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for (int i = 0; i < v->implied_mrf_writes(inst); i++) {
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add_dep(last_mrf_write[inst->base_mrf + i], n);
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last_mrf_write[inst->base_mrf + i] = n;
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}
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for (int i = 0; i < v->implied_mrf_writes(inst); i++) {
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add_dep(last_mrf_write[inst->base_mrf + i], n);
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last_mrf_write[inst->base_mrf + i] = n;
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}
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}
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if (inst->writes_flag()) {
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add_dep(last_conditional_mod[inst->flag_subreg], n, 0);
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last_conditional_mod[inst->flag_subreg] = n;
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add_dep(last_conditional_mod[inst->flag_subreg], n, 0);
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last_conditional_mod[inst->flag_subreg] = n;
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}
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if (inst->writes_accumulator_implicitly(v->brw) &&
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@ -912,14 +912,14 @@ fs_instruction_scheduler::calculate_deps()
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exec_node *node;
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exec_node *prev;
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for (node = instructions.get_tail(), prev = node->prev;
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!node->is_head_sentinel();
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node = prev, prev = node->prev) {
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!node->is_head_sentinel();
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node = prev, prev = node->prev) {
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schedule_node *n = (schedule_node *)node;
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fs_inst *inst = (fs_inst *)n->inst;
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/* write-after-read deps. */
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for (int i = 0; i < inst->sources; i++) {
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if (inst->src[i].file == GRF) {
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if (inst->src[i].file == GRF) {
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if (post_reg_alloc) {
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for (int r = 0; r < inst->regs_read(v, i); r++)
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add_dep(n, last_grf_write[inst->src[i].reg + r]);
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@ -928,10 +928,10 @@ fs_instruction_scheduler::calculate_deps()
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add_dep(n, last_grf_write[inst->src[i].reg * 16 + inst->src[i].reg_offset + r]);
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}
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}
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} else if (inst->src[i].file == HW_REG &&
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(inst->src[i].fixed_hw_reg.file ==
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BRW_GENERAL_REGISTER_FILE)) {
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if (post_reg_alloc) {
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} else if (inst->src[i].file == HW_REG &&
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(inst->src[i].fixed_hw_reg.file ==
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BRW_GENERAL_REGISTER_FILE)) {
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if (post_reg_alloc) {
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int size = reg_width;
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if (inst->src[i].fixed_hw_reg.vstride == BRW_VERTICAL_STRIDE_0)
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size = 1;
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@ -943,27 +943,27 @@ fs_instruction_scheduler::calculate_deps()
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} else if (inst->src[i].is_accumulator()) {
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add_dep(n, last_accumulator_write);
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} else if (inst->src[i].file != BAD_FILE &&
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inst->src[i].file != IMM &&
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inst->src[i].file != UNIFORM &&
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inst->src[i].file != IMM &&
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inst->src[i].file != UNIFORM &&
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(inst->src[i].file != HW_REG ||
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inst->src[i].fixed_hw_reg.file != IMM)) {
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assert(inst->src[i].file != MRF);
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add_barrier_deps(n);
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}
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assert(inst->src[i].file != MRF);
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add_barrier_deps(n);
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}
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}
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if (inst->base_mrf != -1) {
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for (int i = 0; i < inst->mlen; i++) {
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/* It looks like the MRF regs are released in the send
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* instruction once it's sent, not when the result comes
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* back.
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*/
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add_dep(n, last_mrf_write[inst->base_mrf + i], 2);
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}
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for (int i = 0; i < inst->mlen; i++) {
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/* It looks like the MRF regs are released in the send
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* instruction once it's sent, not when the result comes
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* back.
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*/
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add_dep(n, last_mrf_write[inst->base_mrf + i], 2);
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}
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}
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if (inst->reads_flag()) {
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add_dep(n, last_conditional_mod[inst->flag_subreg]);
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add_dep(n, last_conditional_mod[inst->flag_subreg]);
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}
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if (inst->reads_accumulator_implicitly()) {
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@ -983,20 +983,20 @@ fs_instruction_scheduler::calculate_deps()
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}
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}
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} else if (inst->dst.file == MRF) {
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int reg = inst->dst.reg & ~BRW_MRF_COMPR4;
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int reg = inst->dst.reg & ~BRW_MRF_COMPR4;
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last_mrf_write[reg] = n;
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last_mrf_write[reg] = n;
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if (is_compressed(inst)) {
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if (inst->dst.reg & BRW_MRF_COMPR4)
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reg += 4;
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else
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reg++;
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if (is_compressed(inst)) {
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if (inst->dst.reg & BRW_MRF_COMPR4)
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reg += 4;
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else
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reg++;
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last_mrf_write[reg] = n;
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}
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last_mrf_write[reg] = n;
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}
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} else if (inst->dst.file == HW_REG &&
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inst->dst.fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) {
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inst->dst.fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) {
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if (post_reg_alloc) {
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for (int r = 0; r < reg_width; r++)
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last_grf_write[inst->dst.fixed_hw_reg.nr + r] = n;
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@ -1006,17 +1006,17 @@ fs_instruction_scheduler::calculate_deps()
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} else if (inst->dst.is_accumulator()) {
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last_accumulator_write = n;
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} else if (inst->dst.file != BAD_FILE) {
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add_barrier_deps(n);
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add_barrier_deps(n);
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}
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if (inst->mlen > 0 && inst->base_mrf != -1) {
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for (int i = 0; i < v->implied_mrf_writes(inst); i++) {
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last_mrf_write[inst->base_mrf + i] = n;
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}
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for (int i = 0; i < v->implied_mrf_writes(inst); i++) {
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last_mrf_write[inst->base_mrf + i] = n;
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}
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}
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if (inst->writes_flag()) {
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last_conditional_mod[inst->flag_subreg] = n;
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last_conditional_mod[inst->flag_subreg] = n;
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}
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if (inst->writes_accumulator_implicitly(v->brw)) {
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@ -1375,7 +1375,7 @@ instruction_scheduler::schedule_instructions(bblock_t *block)
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/* Remove non-DAG heads from the list. */
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foreach_in_list_safe(schedule_node, n, &instructions) {
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if (n->parent_count != 0)
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n->remove();
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n->remove();
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}
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unsigned cand_generation = 1;
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@ -1412,10 +1412,10 @@ instruction_scheduler::schedule_instructions(bblock_t *block)
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* DAG edge as we do so.
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*/
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for (int i = chosen->child_count - 1; i >= 0; i--) {
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schedule_node *child = chosen->children[i];
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schedule_node *child = chosen->children[i];
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child->unblocked_time = MAX2(child->unblocked_time,
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time + chosen->child_latency[i]);
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child->unblocked_time = MAX2(child->unblocked_time,
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time + chosen->child_latency[i]);
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if (debug) {
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fprintf(stderr, "\tchild %d, %d parents: ", i, child->parent_count);
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@ -1423,13 +1423,13 @@ instruction_scheduler::schedule_instructions(bblock_t *block)
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}
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child->cand_generation = cand_generation;
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child->parent_count--;
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if (child->parent_count == 0) {
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child->parent_count--;
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if (child->parent_count == 0) {
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if (debug) {
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fprintf(stderr, "\t\tnow available\n");
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}
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instructions.push_head(child);
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}
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instructions.push_head(child);
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}
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}
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cand_generation++;
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@ -1440,10 +1440,10 @@ instruction_scheduler::schedule_instructions(bblock_t *block)
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*/
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if (brw->gen < 6 && chosen->inst->is_math()) {
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foreach_in_list(schedule_node, n, &instructions) {
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if (n->inst->is_math())
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n->unblocked_time = MAX2(n->unblocked_time,
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time + chosen->latency);
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}
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if (n->inst->is_math())
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n->unblocked_time = MAX2(n->unblocked_time,
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time + chosen->latency);
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}
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}
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}
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