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freedreno/a7xx: Add BV registers for ROQ status

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Add the BV equivalent of various registers used by crashdec to determine
where the SQE (actually now BR) is.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36590>
This commit is contained in:
Connor Abbott 2025-05-30 09:19:24 -04:00 • committed by Marge Bot
parent 88b855ccea
commit f0d7f2174e
1 changed files with 19 additions and 0 deletions
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19
src/freedreno/registers/adreno/a6xx.xml
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@ -462,6 +462,11 @@ by a particular renderpass/blit.
<reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX"/>
<reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX"/>
<reg32 offset="0x0a66" name="CP_BV_RB_RPTR" variants="A7XX"/>
<reg64 offset="0x0a6d" name="CP_BV_IB1_BASE" variants="A7XX"/>
<reg32 offset="0x0a70" name="CP_BV_IB1_REM_SIZE" variants="A7XX"/>
<reg64 offset="0x0a71" name="CP_BV_IB2_BASE" variants="A7XX"/>
<reg32 offset="0x0a74" name="CP_BV_IB2_REM_SIZE" variants="A7XX"/>
<reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX"/>
<reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX"/>
<reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX"/>
@ -470,6 +475,20 @@ by a particular renderpass/blit.
<reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX"/>
<reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX"/>
<reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX"/>
<reg32 offset="0x0a8f" name="CP_BV_ROQ_AVAIL_RB" variants="A7XX-">
<doc>number of remaining dwords incl current dword being consumed?</doc>
<bitfield name="REM" low="16" high="31"/>
</reg32>
<reg32 offset="0x0a90" name="CP_BV_ROQ_AVAIL_IB1" variants="A7XX-">
<doc>number of remaining dwords incl current dword being consumed?</doc>
<bitfield name="REM" low="16" high="31"/>
</reg32>
<reg32 offset="0x0a91" name="CP_BV_ROQ_AVAIL_IB2" variants="A7XX-">
<doc>number of remaining dwords incl current dword being consumed?</doc>
<bitfield name="REM" low="16" high="31"/>
</reg32>
<reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX"/>
<reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX"/>
<reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX"/>