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i965: Use ISL for MOCS rather than open coding it everywhere

Browse source 
The ISL MOCS infrastructure didn't exist when we wrote the i965 code,
but now that it does, we ought to use it, deleting a complicated mess
that was replicated all throughout the codebase.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
This commit is contained in:
Kenneth Graunke 2021-10-19 10:18:43 -07:00 • committed by Marge Bot
parent d9decdb2c4
commit f0a5f10b6c
7 changed files with 26 additions and 135 deletions
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4
src/mesa/drivers/dri/i965/brw_blorp.c
View file

@ -124,8 +124,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
unsigned *level,
unsigned start_layer, unsigned num_layers)
{
const struct intel_device_info *devinfo = &brw->screen->devinfo;
if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
const unsigned num_samples = mt->surf.samples;
for (unsigned i = 0; i < num_layers; i++) {
@ -145,7 +143,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
.buffer = mt->bo,
.offset = mt->offset,
.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
.mocs = brw_get_bo_mocs(devinfo, mt->bo),
.mocs = brw_mocs(&brw->isl_dev, mt->bo),
},
.aux_usage = aux_usage,
.tile_x_sa = mt->level[*level].level_x,

9
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -283,12 +283,6 @@
#define GFX7_SURFACE_ARYSPC_FULL (0 << 10)
#define GFX7_SURFACE_ARYSPC_LOD0 (1 << 10)
/* Surface state DW1 */
#define GFX8_SURFACE_MOCS_SHIFT 24
#define GFX8_SURFACE_MOCS_MASK INTEL_MASK(30, 24)
#define GFX8_SURFACE_QPITCH_SHIFT 0
#define GFX8_SURFACE_QPITCH_MASK INTEL_MASK(14, 0)
/* Surface state DW2 */
#define BRW_SURFACE_HEIGHT_SHIFT 19
#define BRW_SURFACE_HEIGHT_MASK INTEL_MASK(31, 19)
@ -342,9 +336,6 @@
#define GFX8_SURFACE_Y_OFFSET_SHIFT 21
#define GFX8_SURFACE_Y_OFFSET_MASK INTEL_MASK(23, 21)
#define GFX7_SURFACE_MOCS_SHIFT 16
#define GFX7_SURFACE_MOCS_MASK INTEL_MASK(19, 16)
#define GFX9_SURFACE_MIP_TAIL_START_LOD_SHIFT 8
#define GFX9_SURFACE_MIP_TAIL_START_LOD_MASK INTEL_MASK(11, 8)

21
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -376,7 +376,7 @@ brw_emit_depthbuffer(struct brw_context *brw)
ds_offset + brw->isl_dev.ds.depth_offset,
depth_mt->bo, depth_mt->offset, RELOC_WRITE);
info.mocs = brw_get_bo_mocs(devinfo, depth_mt->bo);
info.mocs = brw_mocs(&brw->isl_dev, depth_mt->bo);
view.base_level = depth_irb->mt_level - depth_irb->mt->first_level;
view.base_array_layer = depth_irb->mt_layer;
view.array_len = MAX2(depth_irb->layer_count, 1);
@ -421,7 +421,7 @@ brw_emit_depthbuffer(struct brw_context *brw)
info.stencil_surf = &stencil_mt->surf;
if (!depth_mt) {
info.mocs = brw_get_bo_mocs(devinfo, stencil_mt->bo);
info.mocs = brw_mocs(&brw->isl_dev, stencil_mt->bo);
view.base_level = stencil_irb->mt_level - stencil_irb->mt->first_level;
view.base_array_layer = stencil_irb->mt_layer;
view.array_len = MAX2(stencil_irb->layer_count, 1);
@ -753,6 +753,8 @@ brw_upload_state_base_address(struct brw_context *brw)
* maybe this isn't required for us in particular.
*/
uint32_t mocs = brw_mocs(&brw->isl_dev, NULL);
if (devinfo->ver >= 6) {
const unsigned dc_flush =
devinfo->ver >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
@ -791,24 +793,23 @@ brw_upload_state_base_address(struct brw_context *brw)
* of bounds and returns zero. To work around this, we pin all SBAs
* to the bottom 4GB.
*/
uint32_t mocs_wb = devinfo->ver >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
int pkt_len = devinfo->ver >= 10 ? 22 : (devinfo->ver >= 9 ? 19 : 16);
BEGIN_BATCH(pkt_len);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (pkt_len - 2));
/* General state base address: stateless DP read/write requests */
OUT_BATCH(mocs_wb << 4 | 1);
OUT_BATCH(mocs << 4 | 1);
OUT_BATCH(0);
OUT_BATCH(mocs_wb << 16);
OUT_BATCH(mocs << 16);
/* Surface state base address: */
OUT_RELOC64(brw->batch.state.bo, RELOC_32BIT, mocs_wb << 4 | 1);
OUT_RELOC64(brw->batch.state.bo, RELOC_32BIT, mocs << 4 | 1);
/* Dynamic state base address: */
OUT_RELOC64(brw->batch.state.bo, RELOC_32BIT, mocs_wb << 4 | 1);
OUT_RELOC64(brw->batch.state.bo, RELOC_32BIT, mocs << 4 | 1);
/* Indirect object base address: MEDIA_OBJECT data */
OUT_BATCH(mocs_wb << 4 | 1);
OUT_BATCH(mocs << 4 | 1);
OUT_BATCH(0);
/* Instruction base address: shader kernels (incl. SIP) */
OUT_RELOC64(brw->cache.bo, RELOC_32BIT, mocs_wb << 4 | 1);
OUT_RELOC64(brw->cache.bo, RELOC_32BIT, mocs << 4 | 1);
/* General state buffer size */
OUT_BATCH(0xfffff001);
/* Dynamic state buffer size */
@ -829,8 +830,6 @@ brw_upload_state_base_address(struct brw_context *brw)
}
ADVANCE_BATCH();
} else if (devinfo->ver >= 6) {
uint8_t mocs = devinfo->ver == 7 ? GFX7_MOCS_L3 : 0;
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
OUT_BATCH(mocs << 8 | /* General State Memory Object Control State */

63
src/mesa/drivers/dri/i965/brw_state.h
View file

@ -359,64 +359,11 @@ void gfx8_init_atoms(struct brw_context *brw);
void gfx9_init_atoms(struct brw_context *brw);
void gfx11_init_atoms(struct brw_context *brw);
/* Memory Object Control State:
* Specifying zero for L3 means "uncached in L3", at least on Haswell
* and Baytrail, since there are no PTE flags for setting L3 cacheability.
* On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
* may still respect that.
*/
#define GFX7_MOCS_L3 1
/* Ivybridge only: cache in LLC.
* Specifying zero here means to use the PTE values set by the kernel;
* non-zero overrides the PTE values.
*/
#define IVB_MOCS_LLC (1 << 1)
/* Baytrail only: snoop in CPU cache */
#define BYT_MOCS_SNOOP (1 << 1)
/* Haswell only: LLC/eLLC controls (write-back or uncached).
* Specifying zero here means to use the PTE values set by the kernel,
* which is useful since it offers additional control (write-through
* cacheing and age). Non-zero overrides the PTE values.
*/
#define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
#define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
#define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
/* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
* and let you force write-back (WB) or write-through (WT) caching, or leave
* it up to the page table entry (PTE) specified by the kernel.
*/
#define BDW_MOCS_WB 0x78
#define BDW_MOCS_WT 0x58
#define BDW_MOCS_PTE 0x18
/* Skylake: MOCS is now an index into an array of 62 different caching
* configurations programmed by the kernel.
*/
/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
#define SKL_MOCS_WB (2 << 1)
/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
#define SKL_MOCS_PTE (1 << 1)
/* Cannonlake: MOCS is now an index into an array of 62 different caching
* configurations programmed by the kernel.
*/
/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
#define CNL_MOCS_WB (2 << 1)
/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
#define CNL_MOCS_PTE (1 << 1)
/* Ice Lake uses same MOCS settings as Cannonlake */
/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
#define ICL_MOCS_WB (2 << 1)
/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
#define ICL_MOCS_PTE (1 << 1)
uint32_t brw_get_bo_mocs(const struct intel_device_info *devinfo,
struct brw_bo *bo);
static inline uint32_t
brw_mocs(const struct isl_device *dev, struct brw_bo *bo)
{
return isl_mocs(dev, 0, bo && bo->external);
}
#ifdef __cplusplus
}

27
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View file

@ -55,28 +55,6 @@
#include "brw_defines.h"
#include "brw_wm.h"
static const uint32_t wb_mocs[] = {
[7] = GFX7_MOCS_L3,
[8] = BDW_MOCS_WB,
[9] = SKL_MOCS_WB,
[10] = CNL_MOCS_WB,
[11] = ICL_MOCS_WB,
};
static const uint32_t pte_mocs[] = {
[7] = GFX7_MOCS_L3,
[8] = BDW_MOCS_PTE,
[9] = SKL_MOCS_PTE,
[10] = CNL_MOCS_PTE,
[11] = ICL_MOCS_PTE,
};
uint32_t
brw_get_bo_mocs(const struct intel_device_info *devinfo, struct brw_bo *bo)
{
return (bo && bo->external ? pte_mocs : wb_mocs)[devinfo->ver];
}
static void
get_isl_surf(struct brw_context *brw, struct brw_mipmap_tree *mt,
GLenum target, struct isl_view *view,
@ -180,7 +158,7 @@ brw_emit_surface_state(struct brw_context *brw,
mt->bo, offset, reloc_flags),
.aux_surf = aux_surf, .aux_usage = aux_usage,
.aux_address = aux_offset,
.mocs = brw_get_bo_mocs(devinfo, mt->bo),
.mocs = brw_mocs(&brw->isl_dev, mt->bo),
.clear_color = clear_color,
.use_clear_address = clear_bo != NULL,
.clear_address = clear_offset,
@ -630,7 +608,6 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
unsigned pitch,
unsigned reloc_flags)
{
const struct intel_device_info *devinfo = &brw->screen->devinfo;
uint32_t *dw = brw_state_batch(brw,
brw->isl_dev.ss.size,
brw->isl_dev.ss.align,
@ -646,7 +623,7 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
.format = format,
.swizzle = ISL_SWIZZLE_IDENTITY,
.stride_B = pitch,
.mocs = brw_get_bo_mocs(devinfo, bo));
.mocs = brw_mocs(&brw->isl_dev, bo));
}
static unsigned

14
src/mesa/drivers/dri/i965/genX_blorp_exec.c
View file

@ -196,19 +196,7 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
*/
.reloc_flags = RELOC_32BIT,
#if GFX_VER == 11
.mocs = ICL_MOCS_WB,
#elif GFX_VER == 10
.mocs = CNL_MOCS_WB,
#elif GFX_VER == 9
.mocs = SKL_MOCS_WB,
#elif GFX_VER == 8
.mocs = BDW_MOCS_WB,
#elif GFX_VER == 7
.mocs = GFX7_MOCS_L3,
#elif GFX_VER > 6
#error "Missing MOCS setting!"
#endif
.mocs = brw_mocs(&brw->isl_dev, brw->batch.state.bo),
};
return data;

23
src/mesa/drivers/dri/i965/genX_state_upload.c
View file

@ -254,24 +254,16 @@ genX(emit_vertex_buffer_state)(struct brw_context *brw,
.AddressModifyEnable = true,
#endif
#if GFX_VER >= 6
.MOCS = brw_mocs(&brw->isl_dev, bo),
#endif
#if GFX_VER < 8
.BufferAccessType = step_rate ? INSTANCEDATA : VERTEXDATA,
.InstanceDataStepRate = step_rate,
#if GFX_VER >= 5
.EndAddress = ro_bo(bo, end_offset - 1),
#endif
#endif
#if GFX_VER == 11
.MOCS = ICL_MOCS_WB,
#elif GFX_VER == 10
.MOCS = CNL_MOCS_WB,
#elif GFX_VER == 9
.MOCS = SKL_MOCS_WB,
#elif GFX_VER == 8
.MOCS = BDW_MOCS_WB,
#elif GFX_VER == 7
.MOCS = GFX7_MOCS_L3,
#endif
};
@ -879,7 +871,7 @@ genX(emit_index_buffer)(struct brw_context *brw)
*/
ib.BufferStartingAddress = ro_32_bo(brw->ib.bo, 0);
#if GFX_VER >= 8
ib.MOCS = GFX_VER >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
ib.MOCS = brw_mocs(&brw->isl_dev, brw->ib.bo);
ib.BufferSize = brw->ib.size;
#else
ib.BufferEndingAddress = ro_bo(brw->ib.bo, brw->ib.size - 1);
@ -3082,7 +3074,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw)
const struct intel_device_info *devinfo = &brw->screen->devinfo;
struct gl_context *ctx = &brw->ctx;
UNUSED uint32_t mocs = GFX_VER < 8 ? GFX7_MOCS_L3 : 0;
UNUSED uint32_t mocs = brw_mocs(&brw->isl_dev, NULL);
struct brw_stage_state *stage_states[] = {
&brw->vs.base,
@ -3677,7 +3669,6 @@ genX(upload_3dstate_so_buffers)(struct brw_context *brw)
#else
struct brw_transform_feedback_object *brw_obj =
(struct brw_transform_feedback_object *) xfb_obj;
uint32_t mocs_wb = GFX_VER >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
#endif
/* Set up the up to 4 output buffers. These are the ranges defined in the
@ -3713,7 +3704,7 @@ genX(upload_3dstate_so_buffers)(struct brw_context *brw)
sob.SOBufferEnable = true;
sob.StreamOffsetWriteEnable = true;
sob.StreamOutputBufferOffsetAddressEnable = true;
sob.MOCS = mocs_wb;
sob.MOCS = brw_mocs(&brw->isl_dev, bo);
sob.SurfaceSize = MAX2(xfb_obj->Size[i] / 4, 1) - 1;
sob.StreamOutputBufferOffsetAddress =