From f04bb4946513b5b6672f1f56fed1bd1c51604cf4 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 10 Jun 2024 14:31:26 -0700 Subject: [PATCH] intel/brw: Delete SAD2 and SADA2 opcodes These were removed with Icelake. While they technically still exist on Skylake, which this compiler supports, we have never used these opcodes in the 14 years we could have done so. So just scrap them. Reviewed-by: Matt Turner Part-of: --- src/intel/compiler/brw_eu.c | 2 -- src/intel/compiler/brw_eu_defines.h | 2 -- src/intel/compiler/brw_eu_validate.c | 1 - src/intel/compiler/brw_fs.cpp | 2 -- src/intel/compiler/brw_fs_builder.h | 2 -- src/intel/compiler/brw_fs_lower_simd_width.cpp | 1 - src/intel/compiler/brw_gram.y | 10 +--------- src/intel/compiler/brw_ir_performance.cpp | 2 -- src/intel/compiler/brw_lex.l | 2 -- src/intel/compiler/brw_shader.cpp | 1 - 10 files changed, 1 insertion(+), 24 deletions(-) diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c index cd12f2672fa..ba5779f26ea 100644 --- a/src/intel/compiler/brw_eu.c +++ b/src/intel/compiler/brw_eu.c @@ -641,8 +641,6 @@ static const struct opcode_desc opcode_descs[] = { { BRW_OPCODE_CBIT, 77, "cbit", 1, 1, GFX_ALL }, { BRW_OPCODE_ADDC, 78, "addc", 2, 1, GFX_ALL }, { BRW_OPCODE_SUBB, 79, "subb", 2, 1, GFX_ALL }, - { BRW_OPCODE_SAD2, 80, "sad2", 2, 1, GFX_ALL }, - { BRW_OPCODE_SADA2, 81, "sada2", 2, 1, GFX_ALL }, { BRW_OPCODE_ADD3, 82, "add3", 3, 1, GFX_GE(GFX125) }, { BRW_OPCODE_DP4, 84, "dp4", 2, 1, GFX_LT(GFX11) }, { BRW_OPCODE_DPH, 85, "dph", 2, 1, GFX_LT(GFX11) }, diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 422da57051f..05e9fd46c7f 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -223,8 +223,6 @@ enum opcode { BRW_OPCODE_CBIT, BRW_OPCODE_ADDC, BRW_OPCODE_SUBB, - BRW_OPCODE_SAD2, - BRW_OPCODE_SADA2, BRW_OPCODE_ADD3, /* Gen12+ only */ BRW_OPCODE_DP4, BRW_OPCODE_DPH, diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index 50be598dc6a..374d254b4c5 100644 --- a/src/intel/compiler/brw_eu_validate.c +++ b/src/intel/compiler/brw_eu_validate.c @@ -337,7 +337,6 @@ inst_uses_src_acc(const struct brw_isa_info *isa, switch (brw_inst_opcode(isa, inst)) { case BRW_OPCODE_MAC: case BRW_OPCODE_MACH: - case BRW_OPCODE_SADA2: return true; default: break; diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 45369e53647..e19860c434f 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -503,8 +503,6 @@ fs_inst::can_do_cmod() const case BRW_OPCODE_RNDE: case BRW_OPCODE_RNDU: case BRW_OPCODE_RNDZ: - case BRW_OPCODE_SAD2: - case BRW_OPCODE_SADA2: case BRW_OPCODE_SHL: case BRW_OPCODE_SHR: case BRW_OPCODE_SUBB: diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h index 567df523261..c2bb9d82d2a 100644 --- a/src/intel/compiler/brw_fs_builder.h +++ b/src/intel/compiler/brw_fs_builder.h @@ -634,8 +634,6 @@ namespace brw { ALU1(RNDZ) ALU2(ROL) ALU2(ROR) - ALU2(SAD2) - ALU2_ACC(SADA2) ALU2(SEL) ALU2(SHL) ALU2(SHR) diff --git a/src/intel/compiler/brw_fs_lower_simd_width.cpp b/src/intel/compiler/brw_fs_lower_simd_width.cpp index 0ecd7d04231..58b18d53b0d 100644 --- a/src/intel/compiler/brw_fs_lower_simd_width.cpp +++ b/src/intel/compiler/brw_fs_lower_simd_width.cpp @@ -277,7 +277,6 @@ brw_fs_get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) case BRW_OPCODE_FBH: case BRW_OPCODE_FBL: case BRW_OPCODE_CBIT: - case BRW_OPCODE_SAD2: case BRW_OPCODE_MAD: case BRW_OPCODE_LRP: case BRW_OPCODE_ADD3: diff --git a/src/intel/compiler/brw_gram.y b/src/intel/compiler/brw_gram.y index b5880955e8d..6aaa003de4d 100644 --- a/src/intel/compiler/brw_gram.y +++ b/src/intel/compiler/brw_gram.y @@ -196,12 +196,6 @@ i965_asm_binary_instruction(int opcode, case BRW_OPCODE_ROR: brw_ROR(p, dest, src0, src1); break; - case BRW_OPCODE_SAD2: - fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n"); - break; - case BRW_OPCODE_SADA2: - fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n"); - break; case BRW_OPCODE_SUBB: brw_SUBB(p, dest, src0, src1); break; @@ -389,7 +383,7 @@ add_label(struct brw_codegen *p, const char* label_name, enum instr_label_type t %token OR %token PLN POP PUSH %token RET RNDD RNDE RNDU RNDZ ROL ROR -%token SAD2 SADA2 SEL SENDS SENDSC SHL SHR SMOV SUBB SYNC +%token SEL SENDS SENDSC SHL SHR SMOV SUBB SYNC %token SEND_GFX4 SENDC_GFX4 SEND_GFX12 SENDC_GFX12 %token WAIT WHILE %token XOR @@ -783,8 +777,6 @@ binaryopcodes: | PLN | ROL | ROR - | SAD2 - | SADA2 | SUBB ; diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp index a4539f088a6..a413b7b50ee 100644 --- a/src/intel/compiler/brw_ir_performance.cpp +++ b/src/intel/compiler/brw_ir_performance.cpp @@ -301,8 +301,6 @@ namespace { case BRW_OPCODE_ROR: case BRW_OPCODE_ROL: case BRW_OPCODE_SUBB: - case BRW_OPCODE_SAD2: - case BRW_OPCODE_SADA2: case BRW_OPCODE_LINE: case BRW_OPCODE_NOP: case SHADER_OPCODE_CLUSTER_BROADCAST: diff --git a/src/intel/compiler/brw_lex.l b/src/intel/compiler/brw_lex.l index b3091292102..40a5a295381 100644 --- a/src/intel/compiler/brw_lex.l +++ b/src/intel/compiler/brw_lex.l @@ -108,8 +108,6 @@ rndu { yylval.integer = BRW_OPCODE_RNDU; return RNDU; } rndz { yylval.integer = BRW_OPCODE_RNDZ; return RNDZ; } rol { yylval.integer = BRW_OPCODE_ROL; return ROL; } ror { yylval.integer = BRW_OPCODE_ROR; return ROR; } -sad2 { yylval.integer = BRW_OPCODE_SAD2; return SAD2; } -sada2 { yylval.integer = BRW_OPCODE_SADA2; return SADA2; } sel { yylval.integer = BRW_OPCODE_SEL; return SEL; } send { yylval.integer = BRW_OPCODE_SEND; diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 763dce438da..1e628a357c0 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -443,7 +443,6 @@ fs_inst::reads_accumulator_implicitly() const switch (opcode) { case BRW_OPCODE_MAC: case BRW_OPCODE_MACH: - case BRW_OPCODE_SADA2: return true; default: return false;