radv: don't use bit_sizes_int to skip nir_lower_bit_size

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29242>

src/amd/common/nir/ac_nir.c

@@ -340,11 +340,9 @@ ac_nir_optimize_uniform_atomics(nir_shader *nir)
    return progress;
 }
 
-unsigned
-ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data)
+static unsigned
+lower_bit_size_callback(const nir_instr *instr, enum amd_gfx_level chip, bool divergence_known)
 {
-   enum amd_gfx_level chip = *(enum amd_gfx_level *)data;
-
    if (instr->type != nir_instr_type_alu)
       return 0;
    nir_alu_instr *alu = nir_instr_as_alu(instr);
@@ -374,10 +372,10 @@ ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data)
       case nir_op_isign:
       case nir_op_uadd_sat:
       case nir_op_usub_sat:
-         return (bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ? 32 : 0;
+         return (!divergence_known || bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ? 32 : 0;
       case nir_op_iadd_sat:
       case nir_op_isub_sat:
-         return bit_size == 8 || !alu->def.divergent ? 32 : 0;
+         return !divergence_known || bit_size == 8 || !alu->def.divergent ? 32 : 0;
 
       default:
          return 0;
@@ -399,7 +397,7 @@ ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data)
       case nir_op_uge:
       case nir_op_bitz:
       case nir_op_bitnz:
-         return (bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ? 32 : 0;
+         return (!divergence_known || bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ? 32 : 0;
       default:
          return 0;
       }
@@ -408,6 +406,28 @@ ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data)
    return 0;
 }
 
+unsigned
+ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data)
+{
+   enum amd_gfx_level chip = *(enum amd_gfx_level *)data;
+   return lower_bit_size_callback(instr, chip, true);
+}
+
+bool
+ac_nir_might_lower_bit_size(const nir_shader *shader)
+{
+   nir_foreach_function_impl(impl, shader) {
+      nir_foreach_block(block, impl) {
+         nir_foreach_instr(instr, block) {
+            if (lower_bit_size_callback(instr, CLASS_UNKNOWN, false))
+               return true;
+         }
+      }
+   }
+
+   return false;
+}
+
 static unsigned
 align_load_store_size(enum amd_gfx_level gfx_level, unsigned size, bool uses_smem, bool is_shared)
 {

src/amd/common/nir/ac_nir.h

@@ -396,6 +396,9 @@ ac_nir_optimize_uniform_atomics(nir_shader *nir);
 unsigned
 ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data);
 
+bool
+ac_nir_might_lower_bit_size(const nir_shader *shader);
+
 bool
 ac_nir_mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigned bit_size,
                               unsigned num_components, int64_t hole_size,

src/amd/common/nir/ac_nir_lower_ngg.c

@@ -1281,8 +1281,6 @@ add_deferred_attribute_culling(nir_builder *b, nir_cf_list *original_extracted_c
             }
             /* primitive is culled if any plane's clipdist of all vertices are negative */
             accepted_by_clipdist = nir_ieq_imm(b, clipdist_neg_mask, 0);
-
-            b->shader->info.bit_sizes_int |= 8;
          } else {
             accepted_by_clipdist = nir_imm_true(b);
          }

src/amd/vulkan/radv_pipeline.c

@@ -345,9 +345,6 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
          NIR_PASS(_, stage->nir, nir_opt_shrink_stores, !instance->drirc.disable_shrink_image_store);
 
          constant_fold_for_push_const = true;
-
-         /* Gather info again, to update whether 8/16-bit are used. */
-         nir_shader_gather_info(stage->nir, nir_shader_get_entrypoint(stage->nir));
       }
    }
 
@@ -526,7 +523,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
 
    NIR_PASS(_, stage->nir, nir_lower_fp16_casts, nir_lower_fp16_split_fp64);
 
-   if (stage->nir->info.bit_sizes_int & (8 | 16)) {
+   if (ac_nir_might_lower_bit_size(stage->nir)) {
       if (gfx_level >= GFX8)
          nir_divergence_analysis(stage->nir);