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aco: Use only VGPR offset on buffer atomics on GFX6-7

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SGPR offset is not included in the bounds check
according to the ISA documentation of GFX6-7 and
indeed it can trigger VM faults on OOB access.

Note that ACO already doesn't use the SGPR offset
on GFX6-7 for buffer loads and stores. This commit
just does the same for buffer atomics.

This commit mitigates a ton of VM faults that are exposed by:
24e75fea4b

Fossil DB stats on Hawaii (GFX7):

Totals from 148 (0.24% of 61818) affected shaders:
Instrs: 324004 -> 327352 (+1.03%)
CodeSize: 1556468 -> 1514100 (-2.72%); split: -2.74%, +0.02%
Latency: 1271480 -> 1276894 (+0.43%)
InvThroughput: 396850 -> 397740 (+0.22%)
VClause: 6861 -> 6858 (-0.04%)
Copies: 34083 -> 37430 (+9.82%)
PreVGPRs: 5705 -> 5706 (+0.02%)
VALU: 147529 -> 150898 (+2.28%)
SALU: 98194 -> 98172 (-0.02%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38958>
This commit is contained in:
Timur Kristóf 2025-12-03 11:52:12 +01:00 • committed by Marge Bot
parent 42e797b139
commit f001515c87
1 changed files with 6 additions and 0 deletions
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6
src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp
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@ -2359,6 +2359,12 @@ visit_atomic_ssbo(isel_context* ctx, nir_intrinsic_instr* instr)
Temp rsrc = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
Temp dst = get_ssa_temp(ctx, &instr->def);
/* GFX6-7 are affected by a hw bug that prevents address clamping to
* work correctly when the SGPR offset is used.
*/
if (offset.type() == RegType::sgpr && ctx->options->gfx_level < GFX8)
offset = as_vgpr(ctx, offset);
aco_opcode op = instr->def.bit_size == 32 ? op32 : op64;
aco_ptr<Instruction> mubuf{create_instruction(op, Format::MUBUF, 6, return_previous ? 1 : 0)};
mubuf->operands[0] = Operand(rsrc);