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intel: Rename IS_GEN* macros to IS_GFX_VER*

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Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "IS_GEN" -rIl $SEARCH_PATH | xargs sed -ie "s/IS_GEN/IS_GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
This commit is contained in:
Anuj Phogat 2021-03-30 10:43:38 -07:00 • committed by Marge Bot
parent e7e55af4d6
commit efc863f9a1
1 changed files with 5 additions and 5 deletions
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10
src/mesa/drivers/dri/i965/genX_pipe_control.c
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@ -63,8 +63,8 @@ get_post_sync_flags(enum pipe_control_flags flags)
(GFX_VER >= 7 && brw->last_pipeline == BRW_COMPUTE_PIPELINE)
/* Closed interval - GFX_VER \in [x, y] */
#define IS_GEN_BETWEEN(x, y) (GFX_VER >= x && GFX_VER <= y)
#define IS_GENx10_BETWEEN(x, y) \
#define IS_GFX_VER_BETWEEN(x, y) (GFX_VER >= x && GFX_VER <= y)
#define IS_GFX_VERx10_BETWEEN(x, y) \
(GFX_VERx10 >= x && GFX_VERx10 <= y)
/**
@ -136,7 +136,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
* We do these now because they may add post-sync operations or CS stalls.
*/
if (IS_GEN_BETWEEN(8, 10) && (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) {
if (IS_GFX_VER_BETWEEN(8, 10) && (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) {
/* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
*
* "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
@ -219,7 +219,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
/* PIPE_CONTROL page workarounds ------------------------------------- */
if (IS_GEN_BETWEEN(7, 8) && (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE)) {
if (IS_GFX_VER_BETWEEN(7, 8) && (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE)) {
/* From the PIPE_CONTROL page itself:
*
* "IVB, HSW, BDW
@ -312,7 +312,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
assert(non_lri_post_sync_flags != 0);
}
if (IS_GENx10_BETWEEN(60, 75) && (flags & PIPE_CONTROL_TLB_INVALIDATE)) {
if (IS_GFX_VERx10_BETWEEN(60, 75) && (flags & PIPE_CONTROL_TLB_INVALIDATE)) {
/* Project: SNB, IVB, HSW / Argument: TLB inv
*
* "{All SKUs}{All Steppings}: Post-Sync Operation ([15:14] of DW1)