From efc75e13ea13b4b5b76dbb0be846c996b99af5de Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Thu, 11 Feb 2021 12:16:10 +0100 Subject: [PATCH] broadcom/compiler: disallow reading two uniforms in the same instruction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The simulator asserts on this, which can happen if we merge a ldunif (or any other instruction that reads a uniform implicitly) and ldunifa in the same instruction. Reviewed-by: Alejandro Piñeiro Part-of: --- src/broadcom/compiler/qpu_schedule.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/broadcom/compiler/qpu_schedule.c b/src/broadcom/compiler/qpu_schedule.c index 31f707f63d6..a637ec56dcf 100644 --- a/src/broadcom/compiler/qpu_schedule.c +++ b/src/broadcom/compiler/qpu_schedule.c @@ -791,6 +791,22 @@ choose_instruction_to_schedule(const struct v3d_device_info *devinfo, dag.link) { const struct v3d_qpu_instr *inst = &n->inst->qpu; + /* Simulator complains if we have two uniforms loaded in the + * the same instruction, which could happen if we have a ldunif + * or sideband uniform and we pair that with ldunifa. + */ + if (prev_inst) { + if (vir_has_uniform(prev_inst->inst) && + (inst->sig.ldunifa || inst->sig.ldunifarf)) { + continue; + } + if ((prev_inst->inst->qpu.sig.ldunifa || + prev_inst->inst->qpu.sig.ldunifarf) && + vir_has_uniform(n->inst)) { + continue; + } + } + /* Don't choose the branch instruction until it's the last one * left. We'll move it up to fit its delay slots after we * choose it.