diff --git a/src/broadcom/compiler/qpu_schedule.c b/src/broadcom/compiler/qpu_schedule.c
index 31f707f63d6..a637ec56dcf 100644
--- a/src/broadcom/compiler/qpu_schedule.c
+++ b/src/broadcom/compiler/qpu_schedule.c
@@ -791,6 +791,22 @@ choose_instruction_to_schedule(const struct v3d_device_info *devinfo,
                             dag.link) {
                 const struct v3d_qpu_instr *inst = &n->inst->qpu;
 
+                /* Simulator complains if we have two uniforms loaded in the
+                 * the same instruction, which could happen if we have a ldunif
+                 * or sideband uniform and we pair that with ldunifa.
+                 */
+                if (prev_inst) {
+                        if (vir_has_uniform(prev_inst->inst) &&
+                            (inst->sig.ldunifa || inst->sig.ldunifarf)) {
+                                continue;
+                        }
+                        if ((prev_inst->inst->qpu.sig.ldunifa ||
+                             prev_inst->inst->qpu.sig.ldunifarf) &&
+                            vir_has_uniform(n->inst)) {
+                                continue;
+                        }
+                }
+
                 /* Don't choose the branch instruction until it's the last one
                  * left.  We'll move it up to fit its delay slots after we
                  * choose it.