From efb863173e38e860d9f3bee6caca3f0d35374230 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Thu, 9 Apr 2026 13:40:01 +0100 Subject: [PATCH] aco: adjust some gfx_level checks for gfx11.7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Rhys Perry Reviewed-by: Georg Lehmann Reviewed-by: Marek Olšák Part-of: --- src/amd/compiler/aco_assembler.cpp | 4 ++-- .../instruction_selection/aco_select_nir_intrinsics.cpp | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/amd/compiler/aco_assembler.cpp b/src/amd/compiler/aco_assembler.cpp index f7f915b3295..2b9b6c1c449 100644 --- a/src/amd/compiler/aco_assembler.cpp +++ b/src/amd/compiler/aco_assembler.cpp @@ -274,11 +274,11 @@ emit_smem_instruction(asm_context& ctx, std::vector& out, const Instru /* We don't use the NV bit. */ } else { encoding = (0b111101 << 26); - if (ctx.gfx_level <= GFX11_5) + if (ctx.gfx_level < GFX12) encoding |= dlc ? 1 << (ctx.gfx_level >= GFX11 ? 13 : 14) : 0; } - if (ctx.gfx_level <= GFX11_5) { + if (ctx.gfx_level < GFX12) { encoding |= opcode << 18; encoding |= glc ? 1 << (ctx.gfx_level >= GFX11 ? 14 : 16) : 0; } else { diff --git a/src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp b/src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp index 34c85b115a5..d4773d0a6d6 100644 --- a/src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp +++ b/src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp @@ -1970,7 +1970,7 @@ visit_image_store(isel_context* ctx, nir_intrinsic_instr* instr) nir_scalar comp = nir_scalar_resolved(instr->src[3].ssa, i); if (nir_scalar_is_undef(comp)) { dmask &= ~BITFIELD_BIT(i); - } else if (ctx->options->gfx_level <= GFX11_5) { + } else if (ctx->options->gfx_level < GFX12) { if (nir_scalar_is_const(comp) && nir_scalar_as_uint(comp) == 0) dmask &= ~BITFIELD_BIT(i); } else { @@ -4262,9 +4262,9 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) Temp tid = emit_mbcnt(ctx, bld.tmp(v1)); Temp src_lane = bld.vadd32(bld.def(v1), tid, delta); - if (ctx->program->gfx_level >= GFX10 && ctx->program->gfx_level <= GFX11_5 && + if (ctx->program->gfx_level >= GFX10 && ctx->program->gfx_level < GFX12 && cluster_size == 32) { - /* ds_bpermute is restricted to 32 lanes on GFX10-GFX11.5. */ + /* ds_bpermute is restricted to 32 lanes on GFX10-GFX11.7. */ Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand::c32(2u), src_lane); tmp = bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, src);