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radv: Merge the flush bits of CMASK & DCC clear.

Browse source 
Probably won't be much different in practice, but still wrong.

Fixes Coverity issue 1435002.

Not CC'ing to stable since this is only hit if you enable MSAA
DCC via RADV_DEBUG.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
This commit is contained in:
Bas Nieuwenhuizen 2018-06-19 10:05:20 +02:00
parent ed06b1cdca
commit ef79457004
1 changed files with 1 additions and 1 deletions
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2
src/amd/vulkan/radv_meta_clear.c
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@ -1089,7 +1089,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
if (!can_avoid_fast_clear_elim)
need_decompress_pass = true;
flush_bits = radv_clear_dcc(cmd_buffer, iview->image, reset_value);
flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
need_decompress_pass);