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nvc0: properly align NVE4_COMPUTE_MP_TEMP_SIZE
MP_TEMP_SIZE must be aligned to 0x8000, while TEMP_SIZE on NVE4_3D must be aligned to 0x20000, so perform both alignments to be sure we allocate enough space (actually the bo will most likely use 128 KiB pages and not aligning to that would be a waste anyway). Cc: "9.2" mesa-stable@lists.freedesktop.org
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5ffa28df4e
commit
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2 changed files with 3 additions and 2 deletions
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@ -512,6 +512,7 @@ nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
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}
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}
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size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
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size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
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size = align(size, 0x8000);
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size *= screen->mp_count;
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size *= screen->mp_count;
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size = align(size, 1 << 17);
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size = align(size, 1 << 17);
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@ -78,11 +78,11 @@ nve4_screen_compute_setup(struct nvc0_screen *screen,
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*/
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*/
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BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(0)), 3);
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BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(0)), 3);
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PUSH_DATAh(push, screen->tls->size / screen->mp_count);
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PUSH_DATAh(push, screen->tls->size / screen->mp_count);
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PUSH_DATA (push, screen->tls->size / screen->mp_count);
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PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
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PUSH_DATA (push, 0xff);
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PUSH_DATA (push, 0xff);
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BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(1)), 3);
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BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(1)), 3);
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PUSH_DATAh(push, screen->tls->size / screen->mp_count);
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PUSH_DATAh(push, screen->tls->size / screen->mp_count);
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PUSH_DATA (push, screen->tls->size / screen->mp_count);
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PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
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PUSH_DATA (push, 0xff);
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PUSH_DATA (push, 0xff);
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/* Unified address space ? Who needs that ? Certainly not OpenCL.
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/* Unified address space ? Who needs that ? Certainly not OpenCL.
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