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gallium/radeon: add radeon_surf::macro_tile_index

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for indexing cik_macrotile_mode_array

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2016-04-26 18:30:07 +02:00
parent ed4fd542de
commit ef45825708
3 changed files with 20 additions and 0 deletions
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1
src/gallium/drivers/radeon/radeon_winsys.h
View file

@ -388,6 +388,7 @@ struct radeon_surf {
uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
uint32_t pipe_config;
uint32_t num_banks;
uint32_t macro_tile_index;
uint64_t dcc_size;
uint64_t dcc_alignment;

3
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View file

@ -422,6 +422,9 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
surf->macro_tile_index = AddrSurfInfoOut.macroModeIndex;
} else {
surf->macro_tile_index = 0;
}
}
}

16
src/gallium/winsys/radeon/drm/radeon_drm_surface.c
View file

@ -31,6 +31,20 @@
#include <radeon_surface.h>
static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
{
unsigned index, tileb;
tileb = 8 * 8 * surf->bpe;
tileb = MIN2(surf->tile_split, tileb);
for (index = 0; tileb > 64; index++)
tileb >>= 1;
assert(index < 16);
return index;
}
static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
const struct radeon_surf_level *level_ws)
{
@ -129,6 +143,8 @@ static void surf_drm_to_winsys(struct radeon_surf *surf_ws,
surf_ws->stencil_tile_split = surf_drm->stencil_tile_split;
surf_ws->stencil_offset = surf_drm->stencil_offset;
surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
for (i = 0; i < RADEON_SURF_MAX_LEVEL; i++) {
surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i]);
surf_level_drm_to_winsys(&surf_ws->stencil_level[i],