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freedreno: use u_math macros/helpers more
Get rid of a few self-defined macros: ALIGN() -> align() min() -> MIN2() max() -> MAX2() Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
parent
38d8b02eba
commit
eec37f1cdc
6 changed files with 20 additions and 25 deletions
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@ -370,22 +370,22 @@ calculate_tiles(struct fd_context *ctx)
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max_width = 256;
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// }
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bin_w = ALIGN(width, 32);
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bin_h = ALIGN(height, 32);
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bin_w = align(width, 32);
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bin_h = align(height, 32);
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/* first, find a bin width that satisfies the maximum width
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* restrictions:
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*/
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while (bin_w > max_width) {
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nbins_x++;
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bin_w = ALIGN(width / nbins_x, 32);
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bin_w = align(width / nbins_x, 32);
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}
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/* then find a bin height that satisfies the memory constraints:
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*/
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while ((bin_w * bin_h * cpp) > gmem_size) {
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nbins_y++;
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bin_h = ALIGN(height / nbins_y, 32);
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bin_h = align(height / nbins_y, 32);
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}
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DBG("using %d bins of size %dx%d", nbins_x*nbins_y, bin_w, bin_h);
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@ -431,7 +431,7 @@ fd_gmem_render_tiles(struct pipe_context *pctx)
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OUT_RING(ring, gmem->bin_w); /* RB_SURFACE_INFO */
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OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
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A2XX_RB_COLOR_INFO_FORMAT(colorformatx));
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reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(ALIGN(gmem->bin_w * gmem->bin_h, 4));
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reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(align(gmem->bin_w * gmem->bin_h, 4));
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if (pfb->zsbuf)
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reg |= A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
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OUT_RING(ring, reg); /* RB_DEPTH_INFO */
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@ -442,13 +442,13 @@ fd_gmem_render_tiles(struct pipe_context *pctx)
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uint32_t bh = gmem->bin_h;
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/* clip bin height: */
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bh = min(bh, gmem->height - yoff);
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bh = MIN2(bh, gmem->height - yoff);
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for (j = 0; j < gmem->nbins_x; j++) {
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uint32_t bw = gmem->bin_w;
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/* clip bin width: */
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bw = min(bw, gmem->width - xoff);
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bw = MIN2(bw, gmem->width - xoff);
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DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
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bh, yoff, bw, xoff);
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@ -298,7 +298,7 @@ fd_program_emit(struct fd_ringbuffer *ring,
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vs_gprs = (vsi->max_reg < 0) ? 0x80 : vsi->max_reg;
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fs_gprs = (fsi->max_reg < 0) ? 0x80 : fsi->max_reg;
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vs_export = max(1, prog->num_exports) - 1;
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vs_export = MAX2(1, prog->num_exports) - 1;
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A2XX_SQ_PROGRAM_CNTL));
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@ -151,7 +151,7 @@ fd_resource_create(struct pipe_screen *pscreen,
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prsc->screen = pscreen;
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rsc->base.vtbl = &fd_resource_vtbl;
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rsc->pitch = ALIGN(tmpl->width0, 32);
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rsc->pitch = align(tmpl->width0, 32);
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rsc->cpp = util_format_get_blocksize(tmpl->format);
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size = rsc->pitch * tmpl->height0 * rsc->cpp;
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@ -193,7 +193,7 @@ fd_resource_from_handle(struct pipe_screen *pscreen,
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rsc->bo = fd_screen_bo_from_handle(pscreen, handle, &rsc->pitch);
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rsc->base.vtbl = &fd_resource_vtbl;
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rsc->pitch = ALIGN(tmpl->width0, 32);
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rsc->pitch = align(tmpl->width0, 32);
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return prsc;
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}
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@ -238,10 +238,10 @@ emit_constants(struct fd_ringbuffer *ring, uint32_t base,
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while (enabled_mask) {
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unsigned index = ffs(enabled_mask) - 1;
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struct pipe_constant_buffer *cb = &constbuf->cb[index];
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unsigned size = ALIGN(cb->buffer_size, 4) / 4; /* size in dwords */
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unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
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// I expect that size should be a multiple of vec4's:
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assert(size == ALIGN(size, 4));
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assert(size == align(size, 4));
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/* hmm, sometimes we still seem to end up with consts bound,
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* even if shader isn't using them, which ends up overwriting
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@ -417,10 +417,10 @@ fd_state_emit(struct pipe_context *pctx, uint32_t dirty)
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OUT_RING(ring, xy2d(ctx->scissor.maxx, /* PA_SC_WINDOW_SCISSOR_BR */
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ctx->scissor.maxy));
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ctx->max_scissor.minx = min(ctx->max_scissor.minx, ctx->scissor.minx);
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ctx->max_scissor.miny = min(ctx->max_scissor.miny, ctx->scissor.miny);
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ctx->max_scissor.maxx = max(ctx->max_scissor.maxx, ctx->scissor.maxx);
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ctx->max_scissor.maxy = max(ctx->max_scissor.maxy, ctx->scissor.maxy);
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ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, ctx->scissor.minx);
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ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, ctx->scissor.miny);
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ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, ctx->scissor.maxx);
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ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, ctx->scissor.maxy);
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}
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if (dirty & FD_DIRTY_VIEWPORT) {
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@ -57,14 +57,9 @@ extern int fd_mesa_debug;
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debug_printf("%s:%d: "fmt "\n", \
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__FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
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#define ALIGN(v,a) (((v) + (a) - 1) & ~((a) - 1))
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#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
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#define min(a, b) (((a) < (b)) ? (a) : (b))
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#define max(a, b) (((a) > (b)) ? (a) : (b))
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#define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
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static inline uint32_t DRAW(enum pc_di_primtype prim_type,
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@ -55,7 +55,7 @@ static uint32_t reg_alu_src_swiz(struct ir2_register *reg);
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static void * ir2_alloc(struct ir2_shader *shader, int sz)
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{
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void *ptr = &shader->heap[shader->heap_idx];
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shader->heap_idx += ALIGN(sz, 4);
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shader->heap_idx += align(sz, 4);
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return ptr;
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}
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@ -136,7 +136,7 @@ void * ir2_shader_assemble(struct ir2_shader *shader, struct ir2_shader_info *in
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info->regs_written = 0;
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/* we need an even # of CF's.. insert a NOP if needed */
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if (shader->cfs_count != ALIGN(shader->cfs_count, 2))
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if (shader->cfs_count != align(shader->cfs_count, 2))
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ir2_cf_create(shader, NOP);
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/* first pass, resolve sizes and addresses: */
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@ -505,7 +505,7 @@ static void reg_update_stats(struct ir2_register *reg,
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struct ir2_shader_info *info, bool dest)
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{
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if (!(reg->flags & (IR2_REG_CONST|IR2_REG_EXPORT))) {
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info->max_reg = max(info->max_reg, reg->num);
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info->max_reg = MAX2(info->max_reg, reg->num);
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if (dest) {
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info->regs_written |= (1 << reg->num);
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@ -514,7 +514,7 @@ static void reg_update_stats(struct ir2_register *reg,
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* input register that the thread scheduler (presumably?)
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* needs to know about:
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*/
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info->max_input_reg = max(info->max_input_reg, reg->num);
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info->max_input_reg = MAX2(info->max_input_reg, reg->num);
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}
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}
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}
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