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radv: Move the shader type to radv_shader_info

Browse source 
Since the default value is 0, this removes some boilerplate.
Moving it to the shader info also makes it accessible using
radv_shader.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23524>
This commit is contained in:
Konstantin Seurer 2023-06-08 15:22:56 +02:00 • committed by Marge Bot
parent 12d7aaf2b8
commit eeae2fb5c4
8 changed files with 29 additions and 34 deletions
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2
src/amd/vulkan/radv_aco_shader_info.h
View file

@ -60,7 +60,7 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv
ASSIGN_FIELD(cs.subgroup_size);
ASSIGN_FIELD(cs.uses_full_subgroups);
aco_info->gfx9_gs_ring_lds_size = radv->gs_ring_info.lds_size;
aco_info->is_trap_handler_shader = radv_args->type == RADV_SHADER_TYPE_TRAP_HANDLER;
aco_info->is_trap_handler_shader = radv->type == RADV_SHADER_TYPE_TRAP_HANDLER;
aco_info->tcs.tess_input_vertices = radv_key->tcs.tess_input_vertices;
aco_info->image_2d_view_of_3d = radv_key->image_2d_view_of_3d;
aco_info->ps.epilog_pc = radv_args->ps_epilog_pc;

2
src/amd/vulkan/radv_pipeline_compute.c
View file

@ -204,7 +204,7 @@ radv_compute_pipeline_compile(struct radv_compute_pipeline *pipeline, struct rad
false, &cs_stage.info);
radv_declare_shader_args(device, pipeline_key, &cs_stage.info, MESA_SHADER_COMPUTE, MESA_SHADER_NONE,
RADV_SHADER_TYPE_DEFAULT, &cs_stage.args);
&cs_stage.args);
cs_stage.info.user_sgprs_locs = cs_stage.args.user_sgprs_locs;
cs_stage.info.inline_push_constant_mask = cs_stage.args.ac.inline_push_const_mask;

10
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -2183,7 +2183,7 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
if (gfx_level >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) {
radv_declare_shader_args(device, pipeline_key, &stages[MESA_SHADER_TESS_CTRL].info, MESA_SHADER_TESS_CTRL,
MESA_SHADER_VERTEX, RADV_SHADER_TYPE_DEFAULT, &stages[MESA_SHADER_TESS_CTRL].args);
MESA_SHADER_VERTEX, &stages[MESA_SHADER_TESS_CTRL].args);
stages[MESA_SHADER_TESS_CTRL].info.user_sgprs_locs = stages[MESA_SHADER_TESS_CTRL].args.user_sgprs_locs;
stages[MESA_SHADER_TESS_CTRL].info.inline_push_constant_mask =
stages[MESA_SHADER_TESS_CTRL].args.ac.inline_push_const_mask;
@ -2200,7 +2200,7 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
if (gfx_level >= GFX9 && stages[MESA_SHADER_GEOMETRY].nir) {
gl_shader_stage pre_stage = stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
radv_declare_shader_args(device, pipeline_key, &stages[MESA_SHADER_GEOMETRY].info, MESA_SHADER_GEOMETRY,
pre_stage, RADV_SHADER_TYPE_DEFAULT, &stages[MESA_SHADER_GEOMETRY].args);
pre_stage, &stages[MESA_SHADER_GEOMETRY].args);
stages[MESA_SHADER_GEOMETRY].info.user_sgprs_locs = stages[MESA_SHADER_GEOMETRY].args.user_sgprs_locs;
stages[MESA_SHADER_GEOMETRY].info.inline_push_constant_mask =
stages[MESA_SHADER_GEOMETRY].args.ac.inline_push_const_mask;
@ -2213,8 +2213,7 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
}
u_foreach_bit (i, active_nir_stages) {
radv_declare_shader_args(device, pipeline_key, &stages[i].info, i, MESA_SHADER_NONE, RADV_SHADER_TYPE_DEFAULT,
&stages[i].args);
radv_declare_shader_args(device, pipeline_key, &stages[i].info, i, MESA_SHADER_NONE, &stages[i].args);
stages[i].info.user_sgprs_locs = stages[i].args.user_sgprs_locs;
stages[i].info.inline_push_constant_mask = stages[i].args.ac.inline_push_const_mask;
}
@ -2252,9 +2251,10 @@ radv_pipeline_create_gs_copy_shader(struct radv_device *device, struct radv_pipe
gs_copy_stage.info.so = gs_info->so;
gs_copy_stage.info.outinfo = gs_info->outinfo;
gs_copy_stage.info.force_vrs_per_vertex = gs_info->force_vrs_per_vertex;
gs_copy_stage.info.type = RADV_SHADER_TYPE_GS_COPY;
radv_declare_shader_args(device, pipeline_key, &gs_copy_stage.info, MESA_SHADER_VERTEX, MESA_SHADER_NONE,
RADV_SHADER_TYPE_GS_COPY, &gs_copy_stage.args);
&gs_copy_stage.args);
gs_copy_stage.info.user_sgprs_locs = gs_copy_stage.args.user_sgprs_locs;
gs_copy_stage.info.inline_push_constant_mask = gs_copy_stage.args.ac.inline_push_const_mask;

3
src/amd/vulkan/radv_pipeline_rt.c
View file

@ -290,8 +290,7 @@ radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache,
RADV_PIPELINE_RAY_TRACING, false, &stage->info);
/* Declare shader arguments. */
radv_declare_shader_args(device, pipeline_key, &stage->info, stage->stage, MESA_SHADER_NONE,
RADV_SHADER_TYPE_DEFAULT, &stage->args);
radv_declare_shader_args(device, pipeline_key, &stage->info, stage->stage, MESA_SHADER_NONE, &stage->args);
stage->info.user_sgprs_locs = stage->args.user_sgprs_locs;
stage->info.inline_push_constant_mask = stage->args.ac.inline_push_const_mask;

9
src/amd/vulkan/radv_shader.c
View file

@ -2194,9 +2194,10 @@ radv_create_trap_handler_shader(struct radv_device *device)
nir_builder b = radv_meta_init_shader(device, stage, "meta_trap_handler");
info.wave_size = 64;
info.type = RADV_SHADER_TYPE_TRAP_HANDLER;
struct radv_shader_args args;
radv_declare_shader_args(device, &key, &info, stage, MESA_SHADER_NONE, RADV_SHADER_TYPE_TRAP_HANDLER, &args);
radv_declare_shader_args(device, &key, &info, stage, MESA_SHADER_NONE, &args);
struct radv_shader_binary *binary = shader_compile(device, &b.shader, 1, stage, &info, &args, &options);
struct radv_shader *shader = radv_shader_create(device, binary);
@ -2260,8 +2261,7 @@ radv_create_rt_prolog(struct radv_device *device)
struct radv_pipeline_key pipeline_key = {0};
radv_declare_shader_args(device, &pipeline_key, &info, MESA_SHADER_COMPUTE, MESA_SHADER_NONE,
RADV_SHADER_TYPE_DEFAULT, &in_args);
radv_declare_shader_args(device, &pipeline_key, &info, MESA_SHADER_COMPUTE, MESA_SHADER_NONE, &in_args);
radv_declare_rt_shader_args(options.info->gfx_level, &out_args);
info.user_sgprs_locs = in_args.user_sgprs_locs;
@ -2323,8 +2323,7 @@ radv_create_vs_prolog(struct radv_device *device, const struct radv_vs_prolog_ke
struct radv_pipeline_key pipeline_key = {0};
radv_declare_shader_args(device, &pipeline_key, &info, key->next_stage,
key->next_stage != MESA_SHADER_VERTEX ? MESA_SHADER_VERTEX : MESA_SHADER_NONE,
RADV_SHADER_TYPE_DEFAULT, &args);
key->next_stage != MESA_SHADER_VERTEX ? MESA_SHADER_VERTEX : MESA_SHADER_NONE, &args);
info.user_sgprs_locs = args.user_sgprs_locs;
info.inline_push_constant_mask = args.ac.inline_push_const_mask;

7
src/amd/vulkan/radv_shader.h
View file

@ -254,6 +254,12 @@ struct gfx10_ngg_info {
bool max_vert_out_per_gs_instance;
};
enum radv_shader_type {
RADV_SHADER_TYPE_DEFAULT = 0,
RADV_SHADER_TYPE_GS_COPY,
RADV_SHADER_TYPE_TRAP_HANDLER,
};
struct radv_shader_info {
uint64_t inline_push_constant_mask;
bool can_inline_all_push_constants;
@ -279,6 +285,7 @@ struct radv_shader_info {
bool force_vrs_per_vertex;
gl_shader_stage stage;
gl_shader_stage next_stage;
enum radv_shader_type type;
uint32_t user_data_0;
struct {

20
src/amd/vulkan/radv_shader_args.c
View file

@ -137,7 +137,7 @@ declare_vs_specific_input_sgprs(const struct radv_shader_info *info, struct radv
if (info->vs.has_prolog)
add_ud_arg(args, 2, AC_ARG_INT, &args->prolog_inputs, AC_UD_VS_PROLOG_INPUTS);
if (args->type != RADV_SHADER_TYPE_GS_COPY &&
if (info->type != RADV_SHADER_TYPE_GS_COPY &&
(stage == MESA_SHADER_VERTEX || previous_stage == MESA_SHADER_VERTEX)) {
if (info->vs.vb_desc_usage_mask) {
add_ud_arg(args, 1, AC_ARG_CONST_DESC_PTR, &args->ac.vertex_buffers, AC_UD_VS_VERTEX_BUFFERS);
@ -158,7 +158,7 @@ declare_vs_input_vgprs(enum amd_gfx_level gfx_level, const struct radv_shader_in
bool merged_vs_tcs)
{
ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.vertex_id);
if (args->type != RADV_SHADER_TYPE_GS_COPY) {
if (info->type != RADV_SHADER_TYPE_GS_COPY) {
if (info->vs.as_ls || merged_vs_tcs) {
if (gfx_level >= GFX11) {
@ -305,15 +305,13 @@ declare_ngg_sgprs(const struct radv_shader_info *info, struct radv_shader_args *
}
static void
radv_init_shader_args(const struct radv_device *device, gl_shader_stage stage, enum radv_shader_type type,
struct radv_shader_args *args)
radv_init_shader_args(const struct radv_device *device, gl_shader_stage stage, struct radv_shader_args *args)
{
memset(args, 0, sizeof(*args));
args->explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
args->remap_spi_ps_input = !radv_use_llvm_for_stage(device, stage);
args->load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr;
args->type = type;
for (int i = 0; i < MAX_SETS; i++)
args->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
@ -380,7 +378,7 @@ radv_ps_needs_state_sgpr(const struct radv_shader_info *info, const struct radv_
static void
declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key,
const struct radv_shader_info *info, gl_shader_stage stage, gl_shader_stage previous_stage,
enum radv_shader_type type, struct radv_shader_args *args, struct user_sgpr_info *user_sgpr_info)
struct radv_shader_args *args, struct user_sgpr_info *user_sgpr_info)
{
const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
bool needs_view_index = info->uses_view_index;
@ -395,7 +393,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
stage = MESA_SHADER_GEOMETRY;
}
radv_init_shader_args(device, stage, type, args);
radv_init_shader_args(device, stage, args);
if (gl_shader_stage_is_rt(stage)) {
radv_declare_rt_shader_args(gfx_level, args);
@ -688,9 +686,9 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
void
radv_declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key,
const struct radv_shader_info *info, gl_shader_stage stage, gl_shader_stage previous_stage,
enum radv_shader_type type, struct radv_shader_args *args)
struct radv_shader_args *args)
{
declare_shader_args(device, key, info, stage, previous_stage, type, args, NULL);
declare_shader_args(device, key, info, stage, previous_stage, args, NULL);
if (gl_shader_stage_is_rt(stage))
return;
@ -718,7 +716,7 @@ radv_declare_shader_args(const struct radv_device *device, const struct radv_pip
allocate_inline_push_consts(info, &user_sgpr_info);
declare_shader_args(device, key, info, stage, previous_stage, type, args, &user_sgpr_info);
declare_shader_args(device, key, info, stage, previous_stage, args, &user_sgpr_info);
}
void
@ -727,7 +725,7 @@ radv_declare_ps_epilog_args(const struct radv_device *device, const struct radv_
{
const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
radv_init_shader_args(device, MESA_SHADER_FRAGMENT, RADV_SHADER_TYPE_DEFAULT, args);
radv_init_shader_args(device, MESA_SHADER_FRAGMENT, args);
ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_DESC_PTR, &args->ac.ring_offsets);
if (gfx_level < GFX11)

10
src/amd/vulkan/radv_shader_args.h
View file

@ -32,12 +32,6 @@
#include "radv_constants.h"
#include "radv_shader.h"
enum radv_shader_type {
RADV_SHADER_TYPE_DEFAULT,
RADV_SHADER_TYPE_GS_COPY,
RADV_SHADER_TYPE_TRAP_HANDLER,
};
struct radv_shader_args {
struct ac_shader_args ac;
@ -85,7 +79,6 @@ struct radv_shader_args {
bool explicit_scratch_args;
bool remap_spi_ps_input;
bool load_grid_size_from_user_sgpr;
enum radv_shader_type type;
};
static inline struct radv_shader_args *
@ -99,8 +92,7 @@ struct radv_shader_info;
void radv_declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key,
const struct radv_shader_info *info, gl_shader_stage stage,
gl_shader_stage previous_stage, enum radv_shader_type type,
struct radv_shader_args *args);
gl_shader_stage previous_stage, struct radv_shader_args *args);
void radv_declare_ps_epilog_args(const struct radv_device *device, const struct radv_ps_epilog_key *key,
struct radv_shader_args *args);