diff --git a/src/gallium/include/winsys/radeon_winsys.h b/src/gallium/include/winsys/radeon_winsys.h
index 409fb80796f..ce5c2f9141d 100644
--- a/src/gallium/include/winsys/radeon_winsys.h
+++ b/src/gallium/include/winsys/radeon_winsys.h
@@ -743,6 +743,13 @@ struct radeon_winsys {
                        const struct pipe_resource *tex, uint64_t flags,
                        unsigned bpe, enum radeon_surf_mode mode, struct radeon_surf *surf);
 
+   uint64_t (*surface_offset_from_coord)(struct radeon_winsys *rws,
+                                         const struct radeon_info *info,
+                                         const struct radeon_surf *surf,
+                                         const struct pipe_resource *tex,
+                                         unsigned level, unsigned x, unsigned y,
+                                         unsigned layer);
+
    uint64_t (*query_value)(struct radeon_winsys *ws, enum radeon_value_id value);
 
    bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers,
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 856371fb2e9..1b8fd385b5e 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -91,7 +91,35 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
    return ac_compute_surface(aws->addrlib, info, &config, mode, surf);
 }
 
+static uint64_t
+amdgpu_surface_offset_from_coord(struct radeon_winsys *rws,
+                                 const struct radeon_info *info,
+                                 const struct radeon_surf *surf,
+                                 const struct pipe_resource *tex,
+                                 unsigned level, unsigned x,
+                                 unsigned y, unsigned layer)
+{
+   struct amdgpu_winsys *aws = amdgpu_winsys(rws);
+   unsigned samples = MAX2(1, tex->nr_samples);
+
+   const struct ac_surf_info surf_info = {
+      .width = tex->width0,
+      .height = tex->height0,
+      .depth = tex->depth0,
+      .samples = samples,
+      .storage_samples = samples,
+      .levels = tex->last_level + 1,
+      .num_channels = util_format_get_last_component(tex->format) + 1,
+      .array_size = tex->array_size,
+   };
+
+   return ac_surface_addr_from_coord(
+      aws->addrlib, info, surf, &surf_info,
+      level, x, y, layer, tex->target == PIPE_TEXTURE_3D);
+}
+
 void amdgpu_surface_init_functions(struct amdgpu_screen_winsys *sws)
 {
    sws->base.surface_init = amdgpu_surface_init;
+   sws->base.surface_offset_from_coord = amdgpu_surface_offset_from_coord;
 }