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i965/fs: Properly precolor payload registers on GEN5 in SIMD16

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For GEN6 SIMD16 mode, we have to 2-align all the registers, so we only have
the even-numbered ones.  This means that we have to divide the register
number by 2 when we precolor.  This wasn't a problem before because we were
setting up the interference between ra_node registers wrong.  This will be
fixed in the next commit.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand 2014-10-13 19:41:17 -07:00
parent 1988b71655
commit ee65f2b50d
1 changed files with 10 additions and 1 deletions
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11
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
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@ -390,7 +390,16 @@ fs_visitor::setup_payload_interference(struct ra_graph *g,
* The alternative would be to have per-physical-register classes, which
* would just be silly.
*/
ra_set_node_reg(g, first_payload_node + i, i);
if (brw->intelScreen->devinfo->gen <= 5 && dispatch_width == 16) {
/* We have to divide by 2 here because we only have even numbered
* registers. Some of the payload registers will be odd, but
* that's ok because their physical register numbers have already
* been assigned. The only thing this is used for is interference.
*/
ra_set_node_reg(g, first_payload_node + i, i / 2);
} else {
ra_set_node_reg(g, first_payload_node + i, i);
}
}
}