diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp
index 123df9e15aa..3bd7d118aa3 100644
--- a/src/intel/compiler/brw_fs_thread_payload.cpp
+++ b/src/intel/compiler/brw_fs_thread_payload.cpp
@@ -439,12 +439,16 @@ task_mesh_thread_payload::task_mesh_thread_payload(const fs_visitor &v)
    assert(subgroup_id_.file != BAD_FILE);
    extended_parameter_0 = retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD);
 
-   urb_output = v.bld.vgrf(BRW_REGISTER_TYPE_UD);
-   /* In both mesh and task shader payload, lower 16 bits of g0.6 is
-    * an offset within Slice's Local URB, which says where shader is
-    * supposed to output its data.
-    */
-   v.bld.AND(urb_output, brw_ud1_grf(0, 6), brw_imm_ud(0xFFFF));
+   if (v.devinfo->ver >= 20) {
+      urb_output = brw_ud1_grf(1, 0);
+   } else {
+      urb_output = v.bld.vgrf(BRW_REGISTER_TYPE_UD);
+      /* In both mesh and task shader payload, lower 16 bits of g0.6 is
+       * an offset within Slice's Local URB, which says where shader is
+       * supposed to output its data.
+       */
+      v.bld.AND(urb_output, brw_ud1_grf(0, 6), brw_imm_ud(0xFFFF));
+   }
 
    if (v.stage == MESA_SHADER_MESH) {
       /* g0.7 is Task Shader URB Entry Offset, which contains both an offset